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Development status :: Beta We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) Adaptive LMS equalizer   Updated on: 25-Apr-2006   VLM: 282 This represent a VHDL implementation of PIPLINED architecture of ADAPTIVE LMS filter. and filter is demostrated to be used as equalizer for removing channel anomalies.   Category :: Communication controller Category :: DSP core Language :: VHDL License :: GPL Phaze :: Design done Development status :: Beta   ae18   Updated on: 11-Oct-2007   VLM: 284 A synthesizable core of the PIC18 cpu. It is capable of executing all PIC18 codes. It has been extensively simulated using Icarus Verilog 0.8.2 and GPLCVER 2.11a to confirm performance. The code is compiled using SDCC 2.5 and GPASM 0.13.4. Synthe...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   aeMB   Updated on: 30-Jul-2008   VLM: 533 A clean room implementation of an EDK3.2 binary compatible Microblaze processor core. It is FPGA proven and has been extensively simulated using Icarus Verilog 0.8.5 and GPLCVER 2.11a to confirm performance. Simulation code is compiled using GCC ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   An Alternative Oscilloscope   Updated on: 29-Oct-2005   VLM: 355 AlternaScope provides a cheap alternative to those pricey oscilloscopes on the market. Using a VGA display and a simple mouse interface, a user can use this scope to look at and measure signals up to about 80Mhz. This kind of scope would be ide...   Category :: Other Language :: Verilog Phaze :: FPGA proven Development status :: Beta   Arm core   Updated on: 26-Apr-2004   VLM: 1085 A free synthesizable arm v4 vhdl model. The framework is made to be extendable for other architectures in the future.   Category :: Microprocessor Category :: SoC Language :: VHDL Development status :: Beta   BigCounter   Updated on: 02-Jan-2008   VLM: 144 Uses the shift register technology to create a big counter, that gives out a pulse at the period specified as a generic.   Category :: Other Language :: VHDL License :: GPL Development status :: Beta   Bluespec Cryptosorter   Updated on: 01-Jul-2008   VLM: 71 This is a crypto sorter. Effectively, it decrypts a database, sorts it and re-encrypts it. A number of highly-reusable IP are present, including a parametric sort module. Project makes use of a number of other open cores and has been proven on...   Language :: Other Phaze :: FPGA proven Development status :: Beta   Bluespec H.264 Decoder   Updated on: 07-Jul-2008   VLM: 649 BSV implementation of H.264 Video decoder.   Category :: Video controller Language :: Other Phaze :: FPGA proven Development status :: Beta   Camellia cores   Updated on: 23-Jun-2008   VLM: 128 VHDL implementations of Camellia cipher. All block size (128, 192, 256) are supported.   Category :: Crypto core Language :: VHDL License :: GPL Development status :: Beta   Cowgirl   Updated on: 31-May-2007   VLM: 322 This is a processor core based on an instruction set I came up with. It's mostly a copy of a MIPS-type RISC architecture. Right now it's in the fairly early stages, but it is working for ~80% of the instructions.   Category :: Microprocessor Language :: VHDL Phaze :: Design done Development status :: Beta   cpu65c02_tc - 65C02 Processor Soft Core with accurate timing   Updated on: 13-Aug-2008   VLM: 489 The 65C02 is the upgraded version of the legendary R6502. cpu65c02_tc offers you an accurate timing for all new and upgraded op codes of the 65C02. This soft core was generated in VHDL and designed with Mentor's HDL Designer. It comes also with ...   Category :: Microprocessor Language :: VHDL License :: GPL Development status :: Beta   DCT - Discrete Cosine Transformer   Updated on: 13-Oct-2001   VLM: 532 Most video compression standards such as HDTV, H.261, JPEG and MPEG use Discrete Cosine Transform (DCT) as a standard transform-coding scheme.   Category :: Arithmetic core Development status :: Beta   Diogenes: Student RISC System   Updated on: 04-Feb-2008   VLM: 202 This Project was developed within a Computer Architecture Course. It demonstrates a simple RISC architecture and features * Assembler * Simulator * Simple I/O (Leds, Buttons, UART, LCD) * VGA Controller Please note that it was developed ...   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Beta   DWT coprocessor on still image   Updated on: 24-Jan-2005   VLM: 130 This core implements Forward and Inverse Discrete Wavelet Transform (FDWT and IDWT) on still image. Wavelet LeGall 5/3 is selected in design. The project is simulated on ModelSim 5.7g and going to implement on Spartan-3 Starter Kit.   Category :: Other Language :: VHDL Development status :: Beta   E1-G.703,G.704,G.706 framer/deframer   Updated on: 03-Jul-2002   VLM: 176 Part of E1 equipment. May be used in E1 MUX and other communication devices with E1 port.   Category :: Communication controller Development status :: Beta   EMPER E123MUX/DEMUX Core   Updated on: 10-Aug-2005   VLM: 80 FEATURES 1. E1 (2048 kbit/s) multiplexer/demultiplexer for ITU-T Recommendations: G.742 (8448 kbit/s E2 frame format) G.751 (34368 kbit/s E3 frame format) 2. Multiplexer/demultiplexer converts: 16 E1s to/from 1 E3 (E13 skip ...   Language :: Verilog Phaze :: FPGA proven Development status :: Beta   Ethernet 10GE MAC   Updated on: 07-Jun-2008   VLM: 361 The 10GE MAC implements the MAC layer for 10Gbps operation as defined in 802.3ae. The MAC is designed to be compact while providing the necessary functionally to be compliant.   Category :: Communication controller Language :: SystemC Language :: Verilog License :: LGPL Standard :: Wishbone compliant core Development status :: Beta   Fast Hadamhard Transforms   Updated on: 20-Apr-2007   VLM: 170 The RTL code calculates the Fast Hadamhard transform(FHT) for a 8-bit input data. This has been coded as per the standard algorithm for FHT. It contains matrix elements addition and subtraction in a definite manner. The RTL code given here is syn...   Category :: DSP core Language :: Verilog Phaze :: Design done Development status :: Beta   Fuzzy Logic Hardware Accelerator   Updated on: 07-Apr-2004   VLM: 153 This project is to design a Fuzzy Logic Hardware Accelerator (FLHA) that is WishBone compatible. FLHA is capable of generating fuzzy rule matrix and inference for it. The input and output data will be 64-bit. Each input and output data will have ...   Category :: Other Language :: VHDL License :: GPL Development status :: Beta   G9 Impulse: Video Game System   Updated on: 16-Dec-2005   VLM: 274 Custom built and designed video game system. Also includes SDK and 'release' title. All designs are open source and specification are free to be modified by the community. Specifications are currently for an early 16 bit system.   Category :: Other Phaze :: FPGA proven Development status :: Beta   Gamepads   Updated on: 15-Sep-2005   VLM: 232 A collection of cores that interface to various gamepads.   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Beta   Graphical LCD interfaces   Updated on: 04-Jan-2004   VLM: 445 This project attempts to write WISHBONE compatible VHDL cores that interface to a wide variety of the most popular LCD controller chips.   Category :: Video controller Standard :: Wishbone compliant core Development status :: Beta   gsc   Updated on: 28-Aug-2007   VLM: 200 gnu systemc compiler - a systemc collection of tools, including a systemc to verilog translator.   Category :: Other Language :: SystemC Language :: Verilog License :: GPL Development status :: Beta Development status :: Production/Stable   HiCoVec - a configurable SIMD CPU   Updated on: 06-Jun-2008   VLM: 215 The HiCoVec processor is based on a simple 32 bit scalar unit and connected with a vector unit for SIMD operations. The amount of data simultaneously processed in the vector unit can be configured as well as the amount of vector registers to h...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Beta   HPC-16   Updated on: 08-Nov-2006   VLM: 152 Simple 16-bit microprocessor, 15-general purpose registers. custom instruction set, load-store RISC but current implementation non piplined, control unit hardwired, 64K address space, total 16-interrupts (10 maskable), memory mapped i/o. design w...   Category :: Microprocessor Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Beta   HyperTransport Tunnel   Updated on: 23-May-2006   VLM: 162 A HyperTransport Tunnel controller written in SystemC. HyperTransport (HT) is a high-performance chip-to-chip interconnect architecture. A tunnel has two HT ports to allow it to be used inside a chain of components.   Category :: Communication controller Language :: Other Phaze :: Design done Development status :: Beta   I/Q Constellation diagram on VGA   Updated on: 02-Mar-2008   VLM: 194 Do you have I/Q digital waveforms in your system ? Do you want to have a quick look at them as a constellation but don't have access to a big lump of equipment ? This block takes in a stream of I/Q pairs, and outputs them in a VGA timing fo...   Category :: Video controller Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Beta   I2C master/slave Core   Updated on: 27-Jun-2008   VLM: 805 The design is capable of working as both I2C compatible master and slave.   Category :: Communication controller Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   I2S to Paralell ADC/DAC controller   Updated on: 20-Dec-2005   VLM: 243 This provides a bridge between a paralell device (such as a microcontroller (uC) and an I2C (!not! I2C) audio bus, generally used for ADC's and DAC's, such as in DVD & MP3 players   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Beta   Image warping/Texture mapping core   Updated on: 02-Aug-2008   VLM: 363 This core maps a texture to an object defined by a grid of control points.   Category :: Video controller Language :: Verilog License :: GPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Beta   Internal Logic State Analyzer   Updated on: 11-Dec-2002   VLM: 193 The internal Logic state Analyser (LA) is a simplified version of a standard logic state analyzer, however it is build-in the prototyped circuit and therefore allows for probing internal signals. The LA at first writes probed signals into its int...   Category :: Prototype board Standard :: Wishbone compliant core Development status :: Beta   LCD Driver   Updated on: 15-Oct-2001   VLM: 558 LCD Driver that we want to designed is a CMOS LCD driver capable of driving a multiplexed display of up to 128 segments ( 16 columns by 8 backplanes ).   Category :: Video controller Development status :: Beta   M1 Core   Updated on: 22-Aug-2008   VLM: 545 The M1 Core is a 32-bit RISC CPU compatible with GCC. It is so simple that it can be used for didactical purposes.   Category :: Microprocessor Language :: Verilog License :: GPL Phaze :: Specification done Development status :: Beta   MiniGA - High Quality PAL Encoder   Updated on: 09-Apr-2007   VLM: 318 The MiniGA is a small graphics adapter for microcontroller which outputs a fully digitally synthesized PAL video signal for TVs, VCRs and video TFTs.   Category :: Video controller Language :: VHDL Development status :: Beta   OFDM modem   Updated on: 19-Apr-2006   VLM: 385 A OFDM modem is the base for the DMT modulation and the 802.g.   Category :: Communication controller Language :: VHDL Development status :: Beta   OpenCores54x DSP   Updated on: 20-Jan-2004   VLM: 447 The OC54x DSP is a cleanroom implementation of a popular family of DSPs.   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Beta   OpenFIRE   Updated on: 16-Oct-2007   VLM: 404 The OpenFire soft processor is an open source Verilog implementation of the Xilinx MicroBlaze. Like the MicroBlaze, the OpenFire is a 32-bit RISC processor based on the DLX architecture by Hennessy and Patterson. The OpenFire was developed by S...   Category :: Microprocessor Category :: SoC Language :: Verilog Phaze :: FPGA proven Development status :: Beta   OpenRISC 2000   Updated on: 20-Jan-2004   VLM: 573 A novel processor architecture based on dataflow architecture techniques and with support for SMT is proposed. Analysis indicates that instructions are normally not dependent on all registers in register file. Since there are many hazards due to ...   Category :: Microprocessor Development status :: Beta   Perlilog   Updated on: 06-Mar-2004   VLM: 787 Perlilog is a design tool, whose main target is easy integration of Verilog IP cores for System-on-Chip (SoC) designs. It's also a good starting point for writing scripts which handle Verilog code in general   Category :: Other Development status :: Beta   Picoblaze's Interrupt Controller   Updated on: 22-Dec-2006   VLM: 168 Picoblaze's interrupt controller expands picoblaze's interrupt into n-interrupt sources (up to 8-interrupts are supported). The controller is put as input port. If interrupt occurs, the firmware will need to read this port, do some interrupt ...   Category :: Other Language :: VHDL Phaze :: Design done Development status :: Beta   PIF2WB   Updated on: 07-Aug-2007   VLM: 105 PIF2Wishbone bridge   Category :: SoC Language :: VHDL Phaze :: Design done Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Beta   PLBv46 to Wishbone Bridge   Updated on: 31-Jul-2008   VLM: 346 A simple non-bursting bridge from IBM PLBv46 Bus to Wishbone.   Category :: SoC Language :: VHDL Standard :: Wishbone compliant core Development status :: Beta   Product Code Iterative Decoder   Updated on: 16-Jan-2006   VLM: 98 An iterative decoder for Product Code, this decoder works for two dimensional Product Code.   Category :: ECC core Language :: VHDL Phaze :: Design done Development status :: Beta   PS2 Core   Updated on: 30-Oct-2003   VLM: 263 This is a generic PS/2 UART for adding mice and keyboard to your projects.   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Beta   Raggedstone PCI Spartan-3 board   Updated on: 08-Feb-2007   VLM: 341 This page contains a port of the open pci core ported to Enterpoint's Raggedstone board. The project has been tested under the Linux and Windows versions of the Xilinx ISE. The project tarball includes a Makefile that will generate a working prom...   Category :: Prototype board Language :: Verilog Language :: VHDL License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta   rfid tag and reader   Updated on: 08-Nov-2006   VLM: 195 Verilog version of RFID tag model   Category :: SoC Language :: Verilog License :: GPL Development status :: Beta   RISE Microprocessor   Updated on: 26-Jan-2007   VLM: 174 RISE (Rarest Instruction Set Ever) is a pipelined 16-bit RISC processor with a simple instruction set.   Category :: Microprocessor Language :: VHDL Development status :: Beta   Scalable Arbiter   Updated on: 08-Aug-2008   VLM: 426 A scalable synchronous round-robin arbiter. The arbiter is designed to run at reasonable clock speeds with up to hundreds of request lines, and it grants in just a few clock cycles. The arbiter's interface has individual request and grant lines f...   Category :: Other Language :: Verilog Development status :: Beta   SHA cores   Updated on: 20-May-2004   VLM: 247 This is a collection of SHA(Secure Hash Algorithm) IP cores.   Category :: Crypto core Language :: Verilog License :: LGPL Phaze :: Design done Development status :: Beta   Soft MultiProcessor on FPGA   Updated on: 12-Mar-2008   VLM: 476 DMA is becoming popular for communication between multiprocessors on SoC or FPGA. This design is a template consisting of four Xilinx microblaze processors and external memory controller connected by a central DMA engine. Compared to fixed bus, F...   Category :: SoC Language :: VHDL License :: GPL Development status :: Beta   SPI Flash controller   Updated on: 22-Jun-2007   VLM: 428 This VHDL module implements a state controller for a serial (SPI) Flash ROM.   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Development status :: Beta   SSRAM interface   Updated on: 14-Oct-2001