Research Postgrad. :: Bugtracker

Research Postgrad.

Information:
Type :: REQUEST
Status :: CLOSED
Assigned to ::

Description:
This verilog code is difficult to follow.
It would be very useful if some documentation was given on how to interface to it.
The SJA1000 documentation is good to describe the operation of the IP, but I think some code specific documentation is needed in order for this to be useable.

Regards,
David.

Comments:

,	Nov 20, 2004
Hello! It is difficult to follow the VHDL code so is it possible to supply a block detaild block diagram and description for the code. Thanks very much in advance

Mohor, Igor	Apr 5, 2004
1. For interfacing to the 8051 CPU read the 8051 documentation. 2. For interfacing to the WISHBONE bus read the WISHBONE documentation. 3. For understanding the CAN protocol read the CAN standard (from Bosch). 4. If you believe that additional documentation is needed, feel free to write it. Put inside whatever you believe is good to have or understand. Be usefull to the opencores community. Regards, Igor M. (The CAN core author)

Mohor, Igor

Apr 5, 2004

1. For interfacing to the 8051 CPU read the 8051 documentation.
2. For interfacing to the WISHBONE bus read the WISHBONE documentation.
3. For understanding the CAN protocol read the CAN standard (from Bosch).
4. If you believe that additional documentation is needed, feel free to write it. Put inside whatever you believe is good to have or understand. Be usefull to the opencores community.

Regards,
Igor M. (The CAN core author)