Is the VHDL version not tested at all?
Information:
Type :: BUG
Status :: CLOSED
Assigned to ::
Description:
Is the VHDL version tested at all? I tried to compile the code with modelsim and I got allot of syntax errors.
ANSWER:
As far as I know the VHDL code was rewritten in VHDL (and is not up-to-date). I know nothing about testing it. Ask the author of the VHDL part.
And please use the cores@opencores.org mailing list for questions. This section is reserved for "BUG reporting".
Regards,
Igor Mohor
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