IRQ reset bug
Information:
Type :: BUG
Status :: CLOSED
Assigned to ::
Description:
Hi
In can_registers.v there was a change in rev 1.33 to make the irq reset one cycle after a read of the irq register.
However, my interpretation of the SJA1000 datasheet is that the IRQ should also clear after a write to 'release receive buffer' (bit 2 of command register).
(see note 2 at the top of page 32 of the data sheet referring to the irq register), specifically: "Giving the command ‘release receive buffer’ will clear RI temporarily"
This is useful if you only active the receive interrupt, in which case it is not necessary to check the irq register, and can just write to release the receive buffer.
Comments:
| Mohor, Igor | Nov 30, 2004 |
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Did you find "the bug" or a re you just thinking about it? If you believe that something is wrong, you can contact me directly. If you did find it (and you can prove it with the test bench), report it here (although I believe you could contact me directly). And now the answer. In the case that a packet is received, RX irq is set. After the "release buffer" command is performed, RX irq is cleared and in the case that another packet is in the buffer, it is set again. The change I did is related to uC that can use only edge triggered interrupts. In the case that irq is already set and another irq is set (for different reason), irq is cleared and set again so an edge is detected.
Please contact me directly if you need further information. Regards, Author (igorm@opencores.org or igor.mohor@gmail.com) |
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