OpenCores

initializing SDRAM's mode register

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Information:
Type :: BUG
Status :: OPENED
Assigned to :: nobody

Description:
If there is no other WB cycles then these which writes into memory controller's registers, initialization of SDRAM's mode register fails. Replacing "if((cs_le_d | rf_we) & wb_cyc_i & wb_stb_i)" (line 424 in "mc_rf.v") with "if(cs_le_d | rf_we)" should solve the problem.

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