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Information:
Type :: REQUEST
Status :: OPENED
Assigned to ::

Description:
I'm synthesize top.v in ps2_soc2.zip found error Compiling include file "../top.v" ERROR:HDLCompilers:26 - ../top.v line 236 expecting '}', found ',' ERROR:HDLCompilers:26 - ../top.v line 236 expecting ';', found ':' ERROR:HDLCompilers:26 - ../top.v line 236 expecting 'end', found '0' ERROR:HDLCompilers:26 - ../top.v line 236 expecting 'end', found ';' ERROR:HDLCompilers:26 - ../top.v line 237 unexpected token: '<=' ERROR:HDLCompilers:26 - ../top.v line 237 unexpected token: '-' ERROR:HDLCompilers:26 - ../top.v line 237 unexpected token: '[' ERROR:HDLCompilers:26 - ../top.v line 237 unexpected token: '[' Module compiled Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"

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