about the two clocks in the design
Information:
Type :: REQUEST
Status :: OPENED
Assigned to ::
nobody
Description:
Sir, I want to use your UART project to send some data from FPGA to PC via RS 232 bus. I am confused about the two clocks in the design.
As per the documentation I am using BR_Clk_I at 10 MHZ for baud rate of 38400. But what clock should I put for WB_CLK_I.Is this clock completely independent of the BR_CLK_I?
Also I couldnt get any information about the following ports in the documentation.
WB_STB_I and WB_ACK_O. Can you please explain their use?
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