SPI Master/Slave Interface

The MOSI circuit of the spi_master core was verified in silicon for up to 50MHz SPI clock, in a 100MHz Spartan-6. Timing analysis show that it may go up to 150MHz. This is very useful for output-only high speed ports. Now the MISO has to be verified for its top speed.

After that, a ARM uC will be the reference testing interface, running SSP at 36MHz.

MISO/MOSI operation was verified in an Digilent Atlys board, using both SPI_MASTER and SPI_SLAVE cores in loopback. The SPI clock tested was 50MHz, with perfect clock phasing.