I2C controller core

CTR5:0 and CR2:1 bits are not used for anything, but appear to be read/write bits. Patch below only writes to bits that are used. Synthesizer should then replace the unused bits with '0' and remove the extra flip-flops.

+++ i2c_master_top.v 2012-07-13 10:03:35.080677900 -0500 @@ -192,7 +187,7 @@ case (wb_adr_i) // synopsys parallel_case 3'b000 : prer 7:0 <= #1 wb_dat_i; 3'b001 : prer 15:8 <= #1 wb_dat_i;

•      3'b010 : ctr         <= #1 wb_dat_i;

•             3'b010 : ctr  [ 7:6] <= #1 wb_dat_i[7:6];

  3'b011 : txr <= #1 wb_dat_i; default: ; endcase @@ -205,8 +200,10 @@ cr <= #1 8'h0; else if (wb_wacc) begin

•     if (core_en & (wb_adr_i == 3'b100) )

•       cr <= #1 wb_dat_i;

•            if (core_en & (wb_adr_i == 3'b100) ) begin

•                cr[7:3] <= #1 wb_dat_i[7:3];

•                cr[0]   <= #1 wb_dat_i[0];

•            end
  	    end
  	  else
  	    begin