Amber ARM-compatible core

I tried to synthesis a25_core in a commercial ASIC synthesis tool and I ran into this:

reg load_pc_r = 'd0; | Warning : Ignoring unsynthesizable construct. VLOGPT-37 : Initial value assignment to reg in file './a25_decode.v' on line 187, column 39.

I'd like to use the core if it was ASIC synthesizable.

Thanks, Jim

The code is written for Xilinx FPGA flow. It is up to users to made any modifications needed to support other tool flows. I chose to not have reset logic as this is not necessary for FPGAs and you get a faster design using fewer resources. For ASIC synthesis you do need a reset. This can be added easily. Just made sure you initialise the registers to the correct values following what is defined already in the code.

Can you explain a bit how to eliminate this error?? Please..

Example. If you see something like this in the code;

module example ( input wire i_clk, output reg o_signal = 1'd0, ); reg other = 1'd1; ... endmodule

Those register initial values cannot be alllied to registers in an ASIC because ASIC registers need to be reset to get a known value. Whereas FPGA registers can be given an initial value during configuration.

So you need to replace it with something like this. (You can choose between synchronous and asynchronous reset depending on which is better for your ASIC technology/application. I give an example using async reset).

module example ( input wire i_clk, input wire i_reset, output reg o_signal, ); reg other;

always@(posedge i_clk or posedge i_reset)

endmodule

Sorry pressed enter too soon on previous post;

Here is the example code with the resets added;

module example ( input wire i_clk, input wire i_reset, output reg o_signal, ); reg other;

always@(posedge i_clk or posedge i_reset) if (i_reset) begin o_signal <= 1'd0; other <= 1'd1; end else begin ... end

endmodule

Sorry html interpretation has mangled my code. But hopefully its enough to give you the idea.