Compiler complains about a comma just in front of a rount bracket

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Information:
Type :: BUG
Status :: CLOSED
Assigned to ::

Description:
1.)
The core has probably some syntax errors (with Quartus II) e.g.:

-----xxxx snip xxxx------- file MAC-tx.v
//MAC_rx_flow ,
input [15:0] pause_quanta ,
input pause_quanta_val ,
);
//******************************************************************************
//internal signals
//******************************************************************************

Q2V6.0 SP1 reports:

Error (10170): Verilog HDL syntax error at MAC_tx.v(90)
near text ")"; expecting an identifier, or "input", or "output", or "inout", or "(*"
-----xxxx snip xxxx------- file MAC-tx.v

The comma just before the round bracket is for some Verilog compilers a syntax error (QuartusII ...)

2.)
______________________________________________________________________

in MAC_rx.v compiler reports:

Error (10001): Verilog HDL or VHDL error at MAC_rx.v(106): object pause_quanta declared in a list of port declarations cannot be redeclared within the module body

Error (10001): Verilog HDL or VHDL error at MAC_rx.v(107): object pause_quanta_val declared in a list of port declarations cannot be redeclared within the module body

----- snip ------
output [15:0] pause_quanta ,
output pause_quanta_val ,
----- snip ------
wire [15:0] pause_quanta ;
wire pause_quanta_val ;
----- snip ------
These signals exist as "output" and "wire" (redeclared...), QuartusII does not like it!

Maybe other compilers are more tolerant??
A fix in that direction would be nice.

KInd regards Frank

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