Amber ARM-compatible core
While developing a core for the MiST board i spend 4-5 days hunting down an issue with the Amber23 core. It seems that Altera/Quartus was ignoring initialisers like
output reg moo = 'd0,
I verified that this was not a problem with Xilinx S6 or V5 chips. I wrote a script to auto convert these (and fix some bugs where they were only partially initialised). The patch can be found here. Script can be made available if needed.
Here is the patch.
I believe this probably also fixes the issues the "synthesizable RTL" bug still open.
This should have been raised as a bug rather than a request.
Here is the transform script for anyone else struggling with Altera or if trunk has moved on. Its very rough. was writted to automate a tedious task for me.
I have come across this issue with other projects. Its specifically when output registers are initialised to high 1's instead of zeros. For example, output reg moo = 2'd3,
Quartus ignores the values assigned, and sets them all as zeros. I had a case open with Altera last year but they claim its a feature they chose not to implement, rather than a bug with their tool.
The patch supplied does fix the issue by using an initial statement to set all the values. It works, but isn't very elegant. It would be much cleaner if Altera supported the Verilog language construct of setting values on the output register declaration. Having it all in one line of code is much better. Xilinx do support it.
Generally speaking for this project I made no attempt to make the code compatible with different tools. I chose to focus on supporting one tool flow (Xilinx) to reduce the effort required. I definitely welcome contributions to extend support to other tool flows.
Fair enough. Could you put a note about Altera in the docs to save people going through the pain i did?