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CTRL register bug #1
Open ocghost opened this issue over 16 years ago
ocghost commented over 16 years ago

Bit 0 of the CTRL register has a bug: when it is set by firmware, it can never ever be cleared again. This bit is part of the CHAR_LEN field which, according to the documentation, is R/W. But this is not the case. This means that the amount of data to transfer can never be changed to an even value if it ever gets set to an odd value.

The problem is in spi_top.v. My suggested fix is to change this line:

ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]};

to this:

ctrl[7:0] <= #Tp wb_dat_i[7:0];
federico.aglietti commented almost 14 years ago

I made the same change, you're right!

kai.poggensee commented over 13 years ago

I'd think that, according to spec, bit 7 is RO. So the correct fix would be to use:

ctrl`SPI_CTRL_CHAR_LEN <= #Tp wb_dat_i`SPI_CTRL_CHAR_LEN;

..as otherwise writing to bit 7 will be possible.

What about the author btw.? Is he not actively maintaining the project / adding bugfixes?

supereic commented over 13 years ago

I find the same problem!

manian commented almost 12 years ago

Please fix the bug with the suggested solution (by Poggensee, Kai) and update svn.

ereeves commented almost 11 years ago

I think we can conclude that no one is maintaining this project.

hno commented over 10 years ago

If I am not mistaken the right fix is to simply not assign bit #7 here:

  •      ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]};
  •      ctrl[6:0] <= #Tp wb_dat_i[6:0];
hno commented over 10 years ago

Hmm... the bugtracker ate all of the code.. another attempt.

<pre> - ctrl[7:0] &lt;= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]}; + ctrl[6:0] &lt;= #Tp wb_dat_i[6:0]; </pre>
MegaVolt_ex commented almost 9 years ago

Nordström, Henrik, fix is Ok! :)


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