Improve test bench around Memory functionality
Information:
Type :: REQUEST
Status :: CLOSED
Assigned to ::
Description:
Just 1 exemple,
File : dmem_ctrl.vhd v1.5
153 -- Process dmem_addr_reg
154 --
155 -- Purpose:
156 -- Implements the Data Memory Address Register.
157 -- This register is required to hold the address during a write operation
158 -- as we cannot hold the address in the input register of the
159 -- synchronous RAM (no clock suppression/gating).
160 --
161 -- NOTE: May be obsoleted by clock enable feature of generic RTL RAM.
162 --
163 dmem_addr_reg: process (res_i, clk_i)
164 begin
165 if res_i = res_active_c then
166 dmem_addr_q <= (others => '0');
If I stick always the reset condition (l.165) to true, no test bench detect it.
Can you improve the test env for take care of memory functionality ?
Because there is lot of verification hole around memory features like on dmem_addr, dmem_o or dmem_read ...
Thanks a lot for all your work, and good luck.
Julien
Comments:
| Laeuger, Arnim | Feb 23, 2008 |
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I can't reproduce that a constant reset condition in line 165 passes all tests. Some regression tests fail (e.g. black_box/mov/a_rr/data_00), some timeout (e.g. black_box/xch/rr) when the condition is changed to
165 if true then Wrong functionality on dmem_addr_q is detected in my opinion, or did I miss something in your post? |
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| Laeuger, Arnim | Feb 3, 2008 |
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Thanks for reporting. I'll have a look at this topic within the next days.
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