President
Information:
Type :: BUG
Status :: CLOSED
Assigned to ::
Jüri, Toomessoo
Description:
I recently ported this code to Verilog and it looks like the original design has several bugs:
a) the data is nibble swapped for IO writes
b) the host->peripheral turn-around cycle did not tri-state on the 2nd cycle
c) reset did not set/clr all the signals - this led to extra logic
Comments:
| Toomessoo, Jüri | Feb 26, 2008 |
|---|---|
|
a) The data is swapped so that byte write from OS to LPC bus
will result the MSB to be MSB on IP block out bus b) Yes it didn't change the bus behavior as on second TAR cycle the bus is pulled high anyway but the inconsistency is fixed (output enable does not go high on TAR cycle 2 now) c) made reset to init all signal in lpc_iow block this should not generate extra hw in FPGA bux fix'ed version tag is version_1_4 |
|
Post a comment:
Login to post comments!