Address decoder should gate stb signals, not cyc signals.
Information:
Type :: BUG
Status :: OPENED
Assigned to ::
Description:
According to the Wishbone spec: "A SLAVE shall
respond to other WISHBONE signals only when this [STB_I] is asserted."
Therefore, the bus arbiter should gate the stb_i signals for slave devices to ensure that only the one being addressed responds to the cycle.
The code generated by this script instead gates the cyc_i slave signals. It is therefore incompatible with some Wishbone compliant modules, for example the register banks provided in the Wishbone toolkit package, as these expect the strobe signal to be gated rather than cyc.
I can check in a fix if nobody else is currently working on the module. It is a simple change to the script - instead of assigning the slave_stb_i signals to stb, assign them to stb & slave_ss (where slave_ss is the select signal for that slave device).
There may be a little more to it to ensure this works with all the supported bus topologies.
Regards,
Richard Walker.
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