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or1ksim030 ic not enabled
Information:
Type :: REQUEST
Status :: CLOSED
Assigned to ::
Jeremy, Bennett
Description:
Hi Everybody,
I've been working with or1ksim0.3.0 and found that if I set enabled=1 in sim.cfg "section ic", the ic is still not enabled. I took a look in the sources and found that in icache-model.c::ic_enabled() that only "cpu_state.sprs[SPR_UPR] |= SPR_UPR_ICP" was being set. In ic_simulate_fetch() however, cpu_state.sprs[SPR_SR] & SPR_SR_ICE is also being checked so I added a line to set ICE in ic_enabled().
cpu_state.sprs[SPR_SR] |= SPR_SR_ICE;
The simulator was now reporting IC read: 100% on all fetches. Looking further I found that in ic_end_sec() the line
memset (ic->tags, 0, ic->nsets * ic->nways * sizeof (oraddr_t));
however "0" is a valid tag which explains the 100% hit rate. I changed the memset value to "-1" so as to provide an initialized value of invalid for the cache. The results now appear to show initial access to a fetchaddr to fail, and subsequent access to addresses in the same block to succeed, and a reasonable hit rate.
John Alfredo
Comments:
| Bennett, Jeremy | Apr 20, 2010 |
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I should have added that the use of -1 to invalidate the tags will be committed to SVN very shortly. Jeremy |
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| Bennett, Jeremy | Apr 20, 2010 |
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Hi John I've investigated further, and this fix is only partially correct. You are right that the tags table should be initialized invalidated (-1). In practice it matters little, since any cache management software would invalidate the tags before turning on the cache. The other part of your suggestion is wrong. ic_enabled () is triggered by the "enabled" field in the configuration file, which indicates the presence of an instruction cache. It is up to the software controlling the cache to enable it at the right time. I've checked against the test suite (now we have that working, and this change would break a number of the tests, which all work on the assumption that on reset a cache if present is not enabled in the supervision register. I'm marking this bug closed. If you think this interpretation by Or1ksim is wrong, perhaps you'd start a discussion on the OpenRISC forum. Thanks for reporting the bug Jeremy
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| Bennett, Jeremy | May 18, 2009 |
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Hi John, Thanks for logging this and finding the solution. I'll try to incorporate it in the next release of Or1ksim. Jeremy
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