I2C core and Max Wishbone frequency
Information:
Type :: REQUEST
Status :: CLOSED
Assigned to ::
nobody
Description:
Im using the I2C core on a 100MHz Wishbone bus implemented on ALTERA cycloneII with Quartus 7.2 compiler and I observed a problema in SCL frequency output.
The I2C slave here is a simple PCF8574 device.
I try to set 100KHz SLC clock and ss from your documentation I set:
prescale = 100MHz/(5*100KHz) -1 = 199 (dec) = C7 (hex)
The measured frequency of the scl on the oscilloscope is around 1.5KHz
There is any limit in the implementation related the Wishbone frequency I use that can explain the SCL behaviour ?
regards
Comments:
| Rinaldi, Gerardo | Jul 7, 2009 |
|---|---|
|
I got the problem in my wishbone implementation logic.
Everything works fine with 100MHz clock now. I think you can close this one issue! |
|
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