IO–Link is used predominantly in an industrial environment in automated production for linking sensors and actuators.

Now the IO-Link Consortium and its associated partners only have the know-how of the electronics to build the master and slave devices using the IO protocol.

The document for the IO-Link protocol was only released this year in January.
http://www.io-link.com/
I have been reading the protocol release note for the last 2 weeks and I am finding it really difficult to put together the pieces.

So is there anyone here who is interested in developing an IP Core for IO-Links ?

I want to start with the slave device for the time being !

Greetings,
Debayan Paul
debayanpaul@yahoo.com

Looks like this is something which is done with PLCs and ladder logic. not something where IP core can be made out of. correct me if i'm wrong.

No, u are wrong !

The protocol(slave) stack as well as the controller for IO-Link slave can be implemented as a dedicated ASIC, which should be able to communicate with the master.
That is what exactly I am trying to do right now !

@ Julian (south SWISS Uni.)............

plz communicate with me at deb.ayon24(at.the.rate.of)googlemail(dot)com
For some reason my Yahoo ID is not working. I have some development plans at my end.

cheers,
Debayan Paul

Hi all,


I am at a stage of my development where I have to implement the Frame Handler (obviously using the state-machines concept) !

So I need some suggestions from you guys as to how as frame handler is implemented using VHDL for other data communication protocols ! If I study them, then I'll get a general ideal as to how this is done, and then I'll be implement it for the IO-Link comm. protocol with necessary changes !!

Please suggest me links, ebooks, further readings, etc !!

Thanks in advance,
Debayan

I have had a look at IO-Link some months ago.
Well, of course you can do an Hardware implementation, and it shouldn't be that hard, it is point-to-point after all, so no MAC needed.
The protocol is really slow compared to nowadays clockfrequencies, and can be easily handled in software. I think the communitiy would really like to have an opensource software stack.

But anyway I think it could turn out an interesting project.
Are you planning on making up a development project on opencores or will you develop at home publish it when it is done?

Thomas

Hi Thomas,

Actually this is my master thesis project !

The most basic hardware model, implementing Frame Handler Type-0 will be ready by October (simulation level) !

I am developing it under the umbrella of IMS Chips, Stuttgart, Germany and my University.
I have no problems making the code public if others need it (I'll just have to make it sure if IMS Chips & my Uni are comfortable with this) ! So if I have to publish it here I'll just publish the whole source code will the necessary documentation !

I have a contemporary of mine, Julian, working at South Swiss University. He is using a software stack & using uC and stuff.

Let's see how much I can do till November !

Debayan Paul

Hi all,

I have done the complete modelling, simulation and synthesis of the data link layer for an IO-Link device. But it implements only frame Type-0 (but it is a good start for a complete approach). I didn't have time to implement the higher order frames. My VHDL model obeys all the basic functions defined by the IO-Link protocol specification v.1.0, January 2009.

The h/w max. operating frequency is 73MHz (clock = 20MHz). All hardware constraints have been met.

I am not releasing the VHDL codes here as it is difficult to understand/use them without documentation.

So if anyone wishes to work on the data link layer development of an IO-Link device using a custom approach, then feel free to contact me.

Gruss,
Debayan Paul
debayanpaul@yahoo.com