I'm using the SD Controller and the plbv46_2_wb bridge in my project to interface a SD Card.

When I read my SD Card, I get wrong responses or even no response. I looked at the plb bus and there are read errors on the bus.

The other facts are:
1- the bridge has two inputs for error and retry: WB_ERR_I and WB_RTY_I, but the SD controller core does not provide any thing like those.
2- the timeout values for retry and access is so low (C_WB_ACCESS_TIMEOUT = 16 and C_WB_RETRY_TIMEOUT = 256) and I think that's why I'm getting bad or no responses because the SD card is very slow. I tried to increase them, but not much I got.

Just wondering if anybody has any comment/idea on the above issues.

Thanks
--Amir

Hi.


Try
(while not busy)
cmd55
acmd41
..

From CMD8 you get the check pattern and the voltage bit in the response?

What's you argument for ACMD41? Try to set it to 0.

Can u paste you response from each command also, thanks.

Hello.

Regarding your comments:

"Try
(while not busy)
cmd55
acmd41
..
I'm doing the same.

"From CMD8 you get the check pattern and the voltage bit in the response?" Yes: 0h1AA

"What's you argument for ACMD41? Try to set it to 0." I did, no use. The busy bit is still zero, however I'm getting the voltage window correctly.

"Can u paste you response from each command also"
Here is it comes:

--CMD55: The next command is App. Specific --
Normal Interupt Status register value is = 0x1
Response Register value is = 0x120

-- ACMD41: Asks the SD card to send operating condition --
Normal Interupt Status register value is = 0x1
Response Register value is = 0xFF8000

After ACMD41 reply try to send a reset CMD to the card.
Then run the initialization chain again, but this time don't use an empty argument when sending the ACMD41, instead set one or several of the bits corresponding to the response you got the first time you sent ACMD41.

Tac2,

Thanks. it is working now. In the loop, I set the argument of ACMD41 to a same value like 0 or 0x40000000 for ever.

My other question is about CMD2. Its response has 136 bits. How can I read the all 127 bits od CID? I set the word select in the cmd_setting _reg to 0,1,2,3, but only for the first one I got a response and then others got timeout.

Please let me know and thanks again for your advice.

Yes about CMD2, you cant... As part of the area optimization of the design i removed response register R2-R4. Because the big response i seldome used and the response data is often not useful.

Instead two control bit (word select) was added in the setting register that controls which word of the 127 bit response that you want to write to the R1 Register. The idea was when you want to read a big register you just send the command 4 times and select 1 new word each time.

But it seams like in the initialization sequence the Card doenst accecpt a second CMD2 because its waiting for CMD 3. The only way i can see around this is to reset the card (CMD0) and run the initialization sequence 4 times and select a new word each time.

I have another question about CMD0. If I send it at the first of inititialization, all commands after it get timeout. The same thing happens when I send it during init.,e.g after ACMD41.

The only way I can get it to work is at the end of init: after CMD3. Do you know why? I've set the cmd_setting_reg and argument registers to zero.

Thanks in advance.

No this looks strange, have you tested with different kinds (or brands) of SD-cards?
I never seen this behaviour before, what kind of SD card are you using?

Test using the software_reset register (bit 0 set to 1 for resting 0 to turn it on) to reset the sd-controller and to disable the clock to the card (If using the dynamic clock). Use this after sending the reset

About the brand or make of the card, I'm not sure. It might be Lexar or Dane-elec. I only have this card, so no way to test with different cards.

In terms of reseting the core, this is the sequence of commands I issue:

1- Set timeout value to 0x9C4

2- Disable core: Write 0x1 to Software reset reg

3- Set clock divider (0: Divide sys_clk by 2)

4- Enable core: Write 0x0 to Software reset reg

5- CMD0: cmd_setting and argument are 0.

Hi,

I am trying to implement this code in Altera Cyclone II device.

Has anyone done this before?.....i am getting some synthesis error...

I think i know onething that might casue problem in altera device.

Remove the GO_IDLE signal in the sd_cm_serial_host.
----------------------
ROW 4: module SD_CMD_SERIAL_HOST ( SD_CLK_IN, RST_IN, SETTING_IN,GO_IDLE ,CMD_IN, REQ_IN, ACK_OUT, REQ_OUT,ACK_IN, CMD_OUT, STATUS, cmd_dat_i, cmd_out_o, cmd_oe_o, st_dat_t);

module SD_CMD_SERIAL_HOST ( SD_CLK_IN, RST_IN, SETTING_IN,CMD_IN, REQ_IN, ACK_OUT, REQ_OUT,ACK_IN, CMD_OUT, STATUS, cmd_dat_i, cmd_out_o, cmd_oe_o, st_dat_t);


ROW 200: always @ (posedge SD_CLK_IN or posedge RST_IN or posedge GO_IDLE)
always @ (posedge SD_CLK_IN or posedge RST_IN )

ROW 202: if (RST_IN || GO_IDLE) begin
if (RST_IN ) begin


ROW 213: always @ (posedge SD_CLK_IN or posedge RST_IN or posedge GO_IDLE)
always @ (posedge SD_CLK_IN or posedge RST_IN)

ROW 216: if (RST_IN || GO_IDLE) begin
if (RST_IN) begin

ROW 234: always @ (posedge SD_CLK_IN or posedge RST_IN or posedge GO_IDLE )
always @ (posedge SD_CLK_IN or posedge RST_IN )

ROW 236: if (RST_IN || GO_IDLE ) begin
if (RST_IN ) begin

ROW 283: always @ (posedge SD_CLK_IN or posedge RST_IN or posedge GO_IDLE )
always @ (posedge SD_CLK_IN or posedge RST_IN )

ROW 288-290: else if (GO_IDLE) begin
state end
Remove

297: always @ (posedge SD_CLK_IN or posedge RST_IN or posedge GO_IDLE )
always @ (posedge SD_CLK_IN or posedge RST_IN )

299: if (RST_IN || GO_IDLE ) begin
if (RST_IN ) begin

317-318: if(GO_IDLE) begin
cmd_oe_o=0;
Remove
-------------


Then in the sd_controller_top row 255 where the SD_CMD_SERIAL_HOST instantiates, change the .RST_IN from
.RST_IN (wb_rst_i | software_reset_reg[0]),
->
.RST_IN (wb_rst_i | software_reset_reg[0] | go_idle),

Second change in this module is to remove the GO_IDLE port from the instansation row 257

This is experimental, the sd_cmd_Serial_host will now go back to Init state when a timeout of command occure. Then it will hold the SD bus to 1 for 64 cycler, the SD card shouldn't care about this (it should detect it), but its untested and i cant find anything in the documentation about it.

Synthesis done with the changes suggested....now i have to try and run the software provided on NIOSII....any changes to be made on main.c to run in on nios II??

And i think the NIOS use another byte-endian? Then you might have to change that in the define before synthesise.

In the software i guess u have to change the SD_REG(REG) macro, and instead use the
IOWR_32 and IOR_32, or memory pointers ( but then u have to consider the cache)

And i think the NIOS use another byte-endian? Then you might have to change that in the define before synthesise.

In the software i guess u have to change the SD_REG(REG) macro, and instead use the
IOWR_32 and IOR_32, or memory pointers ( but then u have to consider the cache)