Ladies and Gentlemen,

I am pleased to announce a new project called "CPU_Lecture".

It explains a complete SoC Design (including the tool chain setup) in quite some detail.

And the best of all: everything runs on Linux. No more Windows (thank you so much, Bill, for your valuable contributions so far).

Enjoy!

/// Juergen

Wonderful, it sounds nice. I am waiting impatiently :)
Thanks OpenCores

Thank you!

Is it certain when it starts?

I'm on board and waiting -Lee

 CPU Lecture project

Its alreadt there - see "CPU Lecture" in the SoC Section of "Projects"

/// Juergen

Thanks's........i'll follow it!

Debayan

Patience waiting

For your information I plan to use the CPU_Lecture core for a project with two undergraduate students.
This is the second project you can find here : http://moutou.pagesperso-orange.fr/#English_Projects
The point is there is a PDF document explaining the goal of the project and how to connect hardware.
The goal of the project is not creating or modifying a core but using a core. Thank you to Dr. Juergen Sauermann for this core.
At the moment I am unable to use interrupts with this core.
This project will be finished in April 2011 and I hope to update the pdf document accordingly.

I have worked around the AVR of CPU lecture as mentioned in previous post... but but but...
I would be pleased to contact Juergen Sauermann because I encounter problems during the project.
I suspect core error in test instruction(s) but I cannot correct them alone.

Let me know if anybody knows how to contact Juergen Sauermann

It's possible to contact me directly at serge.moutou "at" univ-reims.fr

As mentionned in previous post, I have worked around AVR core of CPU_Lecture encountering problems sometimes. Because I am working in C language with a very little knowledge of AVR assembly it takes me a long time to search where is the error.
I can claim that the instruction BRGE doesn't work properly in this core. It would be great if someboy confirm or infirm this claim.

To be more precise, it's probably the following both instructions
CP
BRGE
that don't work properly.

In fact two instructions were not properly working :
- cp
- cpc
They didn't set correctly the flag S used by instruction "brge".
I am not able to contact the author of this opencore !!!
Then, I have published a correction but in a French WIKIVERSITE document : http://fr.wikiversity.org/wiki/Very_High_Speed_Integrated_Circuit_Hardware_Description_Language/Embarquer_un_Atmel_ATMega8#Une_correction_partielle_.3F

I have also attached the corresponding file.

I cannot do more at the moment.

I have finally posted an other (better ?) correction in Bugtracker if anybody is interested.

Thank you "Jergen" for the "CPU_Lecture," that's a really good lecture and includes the RTL source examples, which is really important, imho.

I believe there are some lecture sections you could add regarding how to select an instruction set for some given architecture? For example, why or why not, to include bit field operands or string manipulation operands in the selected instruction set?

What's the cost in gates to add instructions for different types of operations, what's the different levels of instructions, and what kind of system are you building if you do or do not need those instructions?

Here's an example: maybe add an explaination of why is it that the BFFFO instruction in the 68K ISA was so important for embedded systems software architecture? Now that would really enhance the cpu_lecture because you could digress into io-bound versus compute-bound systems architecture.

An advanced topic might be: How do you emulate bfffo instruction in the CPU of your choice, i.e. if that instruction is lacking in current ISA's, what's the penalty in software ISR responsiveness?

Conclusion: the cpu_lecture would be enhanced by information regarding how to qualify some arbitrary instruction set against a given system application.