Hi I am using i2c master slave core in verilog , developing an OVM based verification environment around it . The core works fine for Master Slave RX, TX but When I try repeated start or a start again after stop the scl stays in idle and the internal register hold incorrect values.

If anybody has used this core, please do let me know. I am not sure if the core code is incorrect or my verification environment is programming it wrongly.

Pallavi