I dont seem to quite understand why these registers are being removed.
I will paste the 2 programs, as well as the circuit diagram and such.
p.s. Verilog

Error Messages:
Total Number of Removed Registers = 16
I2C:inst3|AddrData[6,13..15] Stuck at GND due to stuck port data_in
I2C:inst3|AddrData[1..3,5] Merged with I2C:inst3|AddrData[7]
InitializeCODEC:inst4|CodecConfigData[6] Stuck at GND due to stuck port data_in
InitializeCODEC:inst4|CodecConfigData[1..3,5] Merged with InitializeCODEC:inst4|CodecConfigData[7]
InitializeCODEC:inst4|CodecConfigAddr[4..6] Stuck at GND due to stuck port data_in


InitializeCODEC.v:
module InitializeCODEC (Clk,I2CBusy,CCAddr,CCData,Signal);
input Clk; //Clock
input I2CBusy; //Check State of I2C

output reg Signal; //Signal to start I2C Tx
output [6:0] CCAddr; //Codec Config Address
output [8:0] CCData; //Codec Config Data

wire outClk; //Clock Set

reg [6:0] CodecConfigAddr;
reg [8:0] CodecConfigData;

reg [6:0] ControlAddresses [10:0]; //CODEC Register Addresses
reg [8:0] ControlData [10:0]; //CODEC Register Input Values

reg [3:0] Counter; //State Counter
reg [8:0] Index; //Config Index

assign CCAddr = CodecConfigAddr;
assign CCData = CodecConfigData;

initial begin
Counter = 0;
Signal = 0;
Index = 0;
CodecConfigAddr = 7'b0000000;
CodecConfigData = 9'b000000000;

//First Set all of the addr,data values.
ControlAddresses[0] = 7'b0001111; //Reset CODEC
ControlAddresses[1] = 7'b0000000; //Left Line In
ControlAddresses[2] = 7'b0000001; //Right Line In
ControlAddresses[3] = 7'b0000010; //Left Headphones Out
ControlAddresses[4] = 7'b0000011; //Right Headphones Out
ControlAddresses[5] = 7'b0000100; //Analogue Audio Path Control
ControlAddresses[6] = 7'b0000101; //Digital Audio Path Control
ControlAddresses[7] = 7'b0000110; //Power Down Control
ControlAddresses[8] = 7'b0000111; //Digital Audio Interface Format
ControlAddresses[9] = 7'b0001000; //Sampling Control
ControlAddresses[10] = 7'b0001001; //Active Control

ControlData[0] = 9'b000000000;
ControlData[1] = 9'b000000000;
ControlData[2] = 9'b000000000;
ControlData[3] = 9'b010101111;
ControlData[4] = 9'b110101111;
ControlData[5] = 9'b000010000;
ControlData[6] = 9'b000000000;
ControlData[7] = 9'b000000000;
ControlData[8] = 9'b000000001;
ControlData[9] = 9'b000000000;
ControlData[10] = 9'b000000001;
end

always @(posedge Clk) begin
case(Counter)
1: begin
if(I2CBusy == 1) begin //If the I2C is currently busy...
Counter = Counter - 1; //Wait...
end
else begin //I2C is not busy...
CodecConfigAddr = ControlAddresses[Index]; //Get Current Address
CodecConfigData = ControlData[Index]; //Get Current Data
end
end

2: begin
Signal = 1; //Signal the I2C (For one Cycle) to begin sending
end

3: begin
Signal = 0; //Stop the signal

if(Index != 10) begin //If we have not finished sending data...
Index = Index + 1; //Increment the Index
Counter = 0; //Go back to 0 to send the next address and data
end
end

4: begin
Counter = Counter - 1; //Idle state.. Wait...
Signal = 0; //Make sure the I2C isnt getting signaled here
end

//Default
default: begin
Counter = Counter;
end
endcase
Counter = Counter + 1; //Increment State
end

endmodule

I2C.v:
module I2C(SData,SClock,Clk,Addr,Data,Start_Signal,Busy);

inout reg SData; //I2C Data Line
output reg SClock; //I2C Clock Line
input Clk; //Internal Clock (27 MHz)
input [6:0] Addr; //Requested Address
input [8:0] Data; //Data To Send
input Start_Signal; //Signal to Begin Sending
output reg Busy; //Signal When Sending to I2C

reg [5:0] Counter; //State Counter
reg [7:0] Index; //Addr/Data Index
reg [7:0] CSBWrite; //Address To Tell Chip, CSB is Write
reg [15:0] AddrData;//Concatenation of Addr and Data

//Initialize All Variables
initial begin
SData = 1; //Pull SData High
SClock = 1; //Pull SClock High
Counter = 32; //Counter = Idle State
Index = 7; //Set Index to MSB of CSBWrite (CSBWrite is sent first)
CSBWrite = 8'b00110100; //Set CSBWrite To Enable Writing Data to Config
AddrData = 0; //Concatenate Address and Data
Busy = 0; //Module is Not Busy At Start
end

always @(posedge Clk)
begin
if(Start_Signal == 1) begin //When signal is received, start I2C Transmission
//Initialize Counter,Index,Busy
Counter = 0;
Index = 7;
Busy = 0;
end

case(Counter) //This state machine will take care of the I2C Transmission. It skips every odd number so it can wait 1 cycle between instructions
0: begin
Busy = 1; //I2C is now busy
AddrData = {Addr,Data}; //Get the address and data
SData = 0; //Pull SData Low
end

2: begin
SClock = 0; //Pull SClock Low
//This signifies opened connection
end

4: begin
SData = CSBWrite[Index]; //Write the current Bit to SData
end

6: begin
SClock = 1; //Pull SClock High
end

8: begin
SClock = 0; //Pull SClock Low
end

10: begin
if(Index == 0) begin //If we have sent all the bits in the current byte...
Index = 15; //Set the Index to the leftmost of the next byte
SData = 1'bz; //Set SData to high z, so chip can write to it
end
else begin //If we havent sent all the data in the current byte...
Index = Index - 1; //Decrement the index
Counter = 3; //Move Back to State 3 to send the next bit
end
end

12: begin
SClock = 1; //Pull SClock High
end

14: begin //Check for ACK
if(SData == 0) begin //ACK Found
SClock = 0; //Pull SClock Low
end
else begin
Counter = 31; //Address Wrong, Go Idle, Didnt Get ACK
end
end

16: begin
SData = AddrData[Index]; //Set SData to current AddrData Bit
end

18: begin
SClock = 1; //Pull SClock High
end

20: begin
SClock = 0; //Pull SClock Low
end

22: begin
if(Index == 8) begin //If we have sent the first byte of the AddrData...
SData = 1'bz; //Set SData to high z to allow for ACK
Counter = 23; //Move to 23
end
else if (Index == 0) begin //If we have sent the last byte of the AddrData...
SData = 1'bz; //Set SData to high z to allow for ACK
Counter = 23; //Move to 23
end
else begin //If we have not finished sending data...
Index = Index - 1; //Decrement the index
Counter = 15; //Go back to 15
end
end

24: begin
SClock = 1; //Pull SClock High
end

26: begin
if(SData == 0) begin //ACK Received
SClock = 0; //Pull SClock Low
if(Index == 8) begin //If we have not send the last byte...
Index = Index - 1; //Decrement Index
Counter = 15; //Go back to 15
end
else begin //If we have finished sending data...
Counter = 27; //Go to 27
end
end
else begin
Counter = 31; //Address Wrong, Go Idle, Didnt Get ACK
end
end

28: begin
SClock = 1; //Pull SClock High
end

30: begin
SData = 1; //Pull SData High
//This signifies finished connection
end

//Idle State
32: begin
Counter = 31; //Stay in Idle State
Busy = 0; //Not Busy Anymore
end

//Default
default: begin
Counter = Counter;
end
endcase
Counter = Counter + 1; //Increment State
end
endmodule

The circuit diagram picture is attached.