I'm trying to compile the Plasma core that is avaliable here in Quartus II to use on an Altera FPGA. But it's giving me the following error:

Error (10481): VHDL Use Clause error at cache.vhd(17): design library "UNISIM" does not contain primary unit "vcomponents"

Does anyone know how to fix it?

Thanks

Since UNISIM is meant for Xilinx, here's some info on how to convert to Altera:

http://www.alteraforum.com/forum/archive/index.php?t-5471.html

You probably don't need this file with the current settings. Unfortunately, the cache code is currently Xilinx specific. Try setting the plasma entity generic 'use_cache' to '0' so that you don't need cache.vhd. Are you trying to use DDR?

Thanks,
Steve Rhoads

Hi, thanks for the reply.

What I did to compile was to comment "use UNISIM.vcomponents.all;" in cache.vhd and also to comment the "cache_xilinx: if memory_type = "XILINX_16X" generate" on the same file. Just select not to use cache did not work on Quartus II

Now I have a question. For the tbench to work, what memory_type should I use? TRI_PORT_X or ALTERA_LPM.

When I try to compile using TRI_PORT_X Quartus II gives memory exceeded.
When I use ALTERA_LPM it seems to compile all but doesn't seem to work as the final compilation only uses 38 registers from the FPGA (less than 1%) which is almost nothing and doesn't work.

Also, is there any other documentation explaining how to compile the HEX files with the compile instructions?

Thanks.

The TRI_PORT_X memory type doesn't use the FPGA's dual port memory. Instead it creates the individual 32 registers so it is less efficient in using the FPGA resources.

I don't know why using ALTERA_LPM is giving you problems. Can you see the size used by each block?

To generate the HEX files, see the "Tools" tab on the Plasma web page: C:\mlite\tools>gmake tohex. The bintohex.c utility program is short but uncommented.

Steve

Hi Steve, thanks for the quick reply. I'm new to OpenCores and new to MIPS on an FPGA.

What I did was to download the files, from the project and get the .vhd files from folder plasma/trunk/vhdl except for ram_xilinx.vhd and add them all to a New Quartus II Project selecting the tbench as the top level entity.

The small changes made to the code were:

tbench.vhd:
- changed the TRI_PORT_X to ALTERA_LPM
- set the log_file to UNUSED
- added logic in and out to the top entity for it to compile
entity tbench is
port ( l_in : in std_logic;
l_out : out std_logic_vector(7 downto 0));
end; --entity tbench

cache.vhd
- commented the "use UNISIM.vcomponents.all;" as it won't compile in Quartus II 9.1
- commented the "cache_xilinx: if memory_type = "XILINX_16X" generate " down to "end generate; --cache_xilinx"
since this was the part that wouldn't compile without the UNISIM.vcomponents.all

mlite_cpu.vhd
- changed XILINX_16X to ALTERA_LPM in line 239 ("component reg_bank / generic(memory_type : string := "ALTERA_LPM");
- changed XILINX_16X to ALTERA_LPM in line 330 ("component mlite_cpu / generic(memory_type : string := ALTERA_LPM";");
- changed XILINX_16X to ALTERA_LPM in line 415 ("component plasma / generic(memory_type : string := "ALTERA_LPM";");

plasma.vhd
- changed XILINX_16X to ALTERA_LPM in line 40 ("entity plasma is / generic(memory_type : string := "ALTERA_LPM";)
- changed XILINX_16X to ALTERA_LPM in line 83 ("component plasma / generic(memory_type : string := "ALTERA_LPM"; ")


plasma_3e.vhd
- changed XILINX_16X to ALTERA_LPM in line 187 ("u1_plama: plasma /generic map (memory_type => "ALTERA_LPM", ")

plasma_if.vhd
- changed XILINX_16X to ALTERA_LPM in line 43 ("component plasma / generic(memory_type : string := "ALTERA_LPM";", ")
- changed XILINX_16X to ALTERA_LPM in line 134 ("u1_plama: plasma / generic map (memory_type => "ALTERA_LPM",")

ram.vhd
- changed XILINX_16X to ALTERA_LPM in line 24 ("entity ram is / generic(memory_type : string := "ALTERA_LPM");")

reg_bank.vhd
- changed XILINX_16X to ALTERA_LPM in line 21 ("entity reg_bank is / generic(memory_type : string := "ALTERA_LPM");")


With all these changes, Quartus II is able to compile the project but it generates almost no circuit. The Logic Utilization is 43 of 72768 ALUTs and 39 of / 72768 Dedicated Logic Registers. The FPGA I'm using is a Stratix II GX EP2SGX90FF1508C3 on a PCIe Develompent Kit.

Also, I've tested all this code in ModelSim and it works fine.

I'd appreciate if you could give me some more advice.

Thanks,
Renato.

Renato,

The top level entity file plasma_if.vhd lets you set the generic value of memory_type. If you set this to "ALTERA_LPM" this value should be cascaded to all of the lower level entities and override the defaults so that you don't have to change all of the files.

Could you please Email me your compile logs at rhoadss@yahoo.com.

Thanks,
Steve