Hi,

I'm designing a system which will include several masters (PCI-Express, VME, memory controller with DMA) and slaves - some of high performance (ADC/DAC core), some of lower (GPIO, I2C, uart).

I know Wishbone is a well adopted standard and I'd like to use it as an FPGA interconnect in my design, but I have few questions:
- is it possible to implement pipelined read/write transactions - e.g. can I put the read addresses few cycles ahead, each address in single clock cycle, and few cycles later receive the requested data (see attached drawing) without violating the wishbone spec?
- is it possible to put some pipelining in the bus matrix without extending the bus cycle - I'll have 3 or 4 masters, each demanding ~= 0.5 GB/s of throughput on 32-bit bus and ~12 slaves. Generating a purely combinatorial crossbar switch is not an option because of clock frequency requirements.

Thanks,
Tomasz Wlostowski