Dear All,

I am trying to understand Richard Herveille's I2C Master Core verilog code.
In i2c_master_bit_ctrl.v, at around line 306, when he detects the start and stop condition,
he uses the code

sta_condition detect falling edge on SDA while SCL is high
sto_condition detect rising edge on SDA while SCL is high

Is there any problem with this code? It seems that the first one is detecting the rising edge and second one is detecting the falling edge, is it wrong?

This is the correct and intended behaviour.
Read the i2c specifications.

Richard

Hey Richard,

Thanks for your reply.
One thing I can't understand is that, in the code it said:
sta_condition
If sSCL is high, then to generate a start condition, sSDA should be low and dSDA should be high, then is it a rising edge instead of falling edge?

It seems that the right hand side of the equation can't show up, I don't know why.
I will look through the code by myself again to see if I can understand it, but if you can give me a hand, that will be a lot help.

Thanks

to detect an edge you use the current and the previous value.
If the previous (delayed) value is a '1' and the current value is a '0', then it's a falling edge.
If the previous (delayed) value is a '0' and the current value is a '1', then it's a rising edge.

Richard

hello sir,
i am beginner and trying to simulate you code can you help how to set values after start running to get result as mentioned in the document example
regards