Makefile (3 kb)

..In jpg attached RTL description of the circuit is provided..

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;

entity mblite_unit is port
...
-- WB-master inputs from the wb-slaves
wbm_dat_i : in std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- databus input
wbm_ack_i : in std_logic; -- buscycle acknowledge input
-- WB-master outputs to the wb-slaves
wbm_adr_o : out std_logic_vector(CFG_DMEM_SIZE - 1 downto 0); -- address bits
wbm_dat_o : out std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- databus output
wbm_we_o : out std_logic; -- write enable output
wbm_stb_o : out std_logic; -- strobe signals
wbm_sel_o : out std_logic_vector(CFG_DMEM_WIDTH/8 - 1 downto 0); -- select output array
wbm_cyc_o : out std_logic -- valid BUS cycle output
...
wbm_adr_o wbm_dat_o wbm_we_o wbm_stb_o wbm_sel_o wbm_cyc_o m_wb_i.dat_i m_wb_i.ack_i m_wb_i.int_i m_wb_i.clk_i m_wb_i.rst_i ...
wb_adapter : core_wb_adapter
port map
(
dmem_i => s_dmem_i(1),
wb_o => m_wb_o,
dmem_o => s_dmem_o(1),
wb_i => m_wb_i
);
...