Hello all,
I'm a new member. I just downloaded a core but I don't know how to add it to my project as an IP core! Can anybody help me?

How to integrate a core into your design depends upon the core.

For the cores I have produced, the first step is to add the Verilog source files from the core into your project. The second step is to "wire them up", connecting the core's interface to your project.

This is also where the wishbone standard comes in, to try to make things so that they have a common interface ... however, even among wishbone components there's enough variability that you'll want to be certain your master matches the core's wishbone slave interface--if that's the type of core you are interfacing with. If it's a simple wishbone core you wish to connect to, you'll find a bit of a discussion, part of a longer thread, here that you can use for reference. (Assumes Wishbone B4, pipelined accesses)

The only core I have that is different, dblclockfft, requires that you build a C++ program (source code provided), run the C++ program (which generates the Verilog), and then connect the Verilog to your project.

Dan

hello
I have almost the same problem. I have designed a network on chip in verilog code in Xilinx Ise. now I want to measure my network performance so I should connect the routers to the IP cores. I wonder if I can find for example x86 core in internet and how I can connect the cores to my routers.
please help me in this issue.

thank you

kian_mary,
Have you considered the v586 core?
Dan