Hi all

After the success of running "Hello world" with minsoc and testing UART with Spartan-3E. Now is turn of Ethernet, when we can now run "hello world" and testing the communication with Ethernet. So the principal steps for this are :

1 ) go and download the latest project of minosoc
http://opencores.com/project,minsoc

2) open the doc Howto and read the steps for simulation and implementation.

So, just 2 steps and you have a SOC running in your board Spartan-3E500 starter Kits.

System Features

-or1200 OpenRISC implementation

-Resizable onchip memory

-System frequency selection

-JTAG debug featuring a multitude of cables

-UART and Ethernet modules

-FPGA independent and dependent code (spartan-3E500) for memory, clock adaptation (DCMs) and JTAG Tap

-System configuration in a single definition file

-Example firmwares using UART and Ethernet

-Testbench included, for the simulation of exactly your configured system.

Many thanks to Raul and good luck.

Hi Bakiri,

I am trying to implement the minsoc with ethernet on my Spartan 3E500 starter kit. I followed the "howto" doc in minsoc project folder. I met this error of "Too many comps of type RAMB16" during the "Map" step in implementation. The Design summary indicates the usage of RAMB16s is 23 while spartan 3E500 only have 20 of them.
Do you have any suggestion of what I should do to meet this limitation?
Thank you very much!

Regards.

Zhengyu

Hi yangz2

first confirm you have do this steps : confirm the first 1)

1) minsoc/rtl/verilog/minsoc_defines.v => change MEMORY_ADR_WIDTH from 13 to 12

2) minsoc/rtl/verilog/or1200/rtl/verilog/or1200_defines.v =>
� uncomment `define OR1200_XILINX_RAMB16
� comment `define OR1200_MULT_IMPLEMENTED
� comment `define OR1200_MAC_IMPLEMENTED
� uncomment `define OR1200_RFRAM_DUALPORT
� comment `define OR1200_RFRAM_GENERIC

3)minsoc/rtl/verilog/ethmac/rtl/verilog/eth_defines.v =>
� uncomment `define ETH_FIFO_XILINX
� uncomment `define ETH_XILINX_RAMB4

4) adv_debug_system => disable jsp in step 5
configure minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
=> comment out line 67, �`define DBG_JSP_SUPPORTED�

thats all, it's work fine

Hi Bakiri:
I am planning to put the minsoc on my spartan 3E-1600 development kit, is there any changes need for it? Or is your spartan-3E 500 or 1600?
Thanks.
B.R
Colin Chen

Hi guys:
I guess your boards are 3E500. Mine is 3E 1600, could you please tell me if i need to do some changes for running the code on the 3E1600 board.
Thanks.
Colin Chen

Hi colin

because you have spartan-3E1600 that is big than 3E500, you can just keep the default configuration like Spartan-3A1800 of Raul (memory and clock)without disabling anything,

the clock are the same for all bord of Spartan-3E and spartan-3A.

there is also a wiki page for minsoc project if you want know more and fix a future problem as adv_debug_system http://minsoc.wikaba.com/

Hi Bakiri:
Thanks for the help. I have programmed the bits into the fpga and run the uart code successfully through the gdb. The feeling is great. Now the next step i am thinking is how to support the external dram on the board, my final goal is to run the linux on the fpga with ethernet/uart.
B.R
Colin Chen

Hello ,

I am trying to implement Minsoc on Spartan 3E 500. I have followed all the steps. I am now having problems with using the Jtag[DLC9] cable for downloading the design. I am using Impact to dowmload the bit file on to the board. After the bit file is downloaded I am unable to use the cable with the adv_jtag_debugger. Could anyone of you please let me know what are the possible options do I have. I want to use the debugger too. I did explore some options which include downloading the file to the SPI memory do that the device can self configure on start up , but I cannot use the debugger with that.

Did anyone of you have sucess using the adv debugger?

Thanks
Prathyusha