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RE: Verilog/VHDL by jamesedgar on Mar 20, 2011			jamesedgar Posts: 8 Joined: Sep 14, 2004 Last seen: May 13, 2012
Kaushik -- The project mentioned in my previous post was set up to be used in a real time video compression system. The code completes a log search of one macroblock every 512 clock cycles. With a clock speed of 54MHz, this can perform motion detection on an NTSC or PAL image with about 1mS of delay from the start of the second frame to the output of the fisrt motion vector for the top row of macroblocks. Multiple tests are being done at the same time comparing the current macroblock to the 9 macroblocks in the same and surrounding positions in the previous image. I assume you are using ARPS with an interest in skipping computations to save time whenever possible. This isn't really a concern with this code. However, if you are trying to find a better match, it might be possible to modify the search vectors based on predicted motion. The log search is done at 36 points, starting with 9 points 8 pixels apart, then 9 more 4 pixels around the best match, then 9 more 2 pixels around that match, and then 9 more surrounding that match. There is also a half pel check. You could certainly start the search somewhere other than the center of the macroblock if you have predicted motion vectors (assuming the search stays in the 48 x 48 pixel search area.) In this case, you might also want to skip the first set of searches that are 8 pixels apart. Several examples in the smaller test project actually don't find the optimum solution because there is a tie in the first log search, and the code takes the first point by default (this is mentioned in the test log.) If the start point was moved closer to the correct solution, the correct solution would probably be found. Adjusting the vertical coordinate would not be too difficult, since this value is used to determine which memory is read from local block ram. miny is the main variable, but there are several temporary copies that you would need to look at. Adjusting the horizontal value would be more difficult. Case statements are used based on the predictable values of minx. Once this was changed, these would all become arrays, and you would likely use even more resources than the project uses now (about half of a Xilinx Spartan 3 1600.) This wouldn't be a problem if your motion vector selected one of the earlier log points, and the tests were just continued from that point. James Kaushik -- The project mentioned in my previous post was set up to be used in a real time video compression system. The code completes a log search of one macroblock every 512 clock cycles. With a clock speed of 54MHz, this can perform motion detection on an NTSC or PAL image with about 1mS of delay from the start of the second frame to the output of the fisrt motion vector for the top row of macroblocks. Multiple tests are being done at the same time comparing the current macroblock to the 9 macroblocks in the same and surrounding positions in the previous image. I assume you are using ARPS with an interest in skipping computations to save time whenever possible. This isn't really a concern with this code. However, if you are trying to find a better match, it might be possible to modify the search vectors based on predicted motion. The log search is done at 36 points, starting with 9 points 8 pixels apart, then 9 more 4 pixels around the best match, then 9 more 2 pixels around that match, and then 9 more surrounding that match. There is also a half pel check. You could certainly start the search somewhere other than the center of the macroblock if you have predicted motion vectors (assuming the search stays in the 48 x 48 pixel search area.) In this case, you might also want to skip the first set of searches that are 8 pixels apart. Several examples in the smaller test project actually don't find the optimum solution because there is a tie in the first log search, and the code takes the first point by default (this is mentioned in the test log.) If the start point was moved closer to the correct solution, the correct solution would probably be found. Adjusting the vertical coordinate would not be too difficult, since this value is used to determine which memory is read from local block ram. miny is the main variable, but there are several temporary copies that you would need to look at. Adjusting the horizontal value would be more difficult. Case statements are used based on the predictable values of minx. Once this was changed, these would all become arrays, and you would likely use even more resources than the project uses now (about half of a Xilinx Spartan 3 1600.) This wouldn't be a problem if your motion vector selected one of the earlier log points, and the tests were just continued from that point. James

RE: Verilog/VHDL by gkamal on Mar 22, 2011			gkamal Posts: 3 Joined: Mar 14, 2011 Last seen: Apr 14, 2011
[q]gkamal I appreciate your interest. but VLSI is very vast. first be clear in which direction u r travelling to.[/q]kowshik.. thank u sir for u r response.in which direction means please can u explain more. now i am doing MTECH vlsi.. gkamal I appreciate your interest. but VLSI is very vast. first be clear in which direction u r travelling to. kowshik.. thank u sir for u r response.in which direction means please can u explain more. now i am doing MTECH vlsi..

RE: Verilog/VHDL by kaushik_mallibhat on Mar 22, 2011			kaushik_mallibhat Posts: 5 Joined: Feb 11, 2011 Last seen: Aug 10, 2011
tats great...! then u have options like going towards analog side if u r interested with. tats great...! then u have options like going towards analog side if u r interested with.

RE: Verilog/VHDL by gkamal on Mar 23, 2011			gkamal Posts: 3 Joined: Mar 14, 2011 Last seen: Apr 14, 2011
can u sugest me some basic books sir... to learn basic... can u sugest me some basic books sir... to learn basic...

RE: Verilog/VHDL by kaushik_mallibhat on Apr 18, 2011			kaushik_mallibhat Posts: 5 Joined: Feb 11, 2011 Last seen: Aug 10, 2011
hello james, i saw the code at this link...http://opencores.org/project,macroblock_motion_detection. can u suggest me how to implement using IP core memory.. hello james, i saw the code at this link...http://opencores.org/project,macroblock_motion_detection. can u suggest me how to implement using IP core memory..

RE: Verilog/VHDL by raveendras4a5 on May 3, 2011			raveendras4a5 Posts: 1 Joined: Nov 24, 2010 Last seen: May 9, 2011
hi, i am doing a projet named "HDB3 ENCODER". i need to design the circuit by verilog program. in that circuit i have D-flip flop block with set and reset inputs. can anyone tell the verilog code to design this block? please...... i am attaching the block figure.[q]<a href="uploads/1304409561_dff.jpg">dff.jpg</a> (5 kb)[/q] hi, i am doing a projet named "HDB3 ENCODER". i need to design the circuit by verilog program. in that circuit i have D-flip flop block with set and reset inputs. can anyone tell the verilog code to design this block? please...... i am attaching the block figure. dff.jpg (5 kb)

RE: Verilog/VHDL by alexx188 on Nov 22, 2011			alexx188 Posts: 1 Joined: May 14, 2011 Last seen: Apr 23, 2012
[q]Altera provides a free version of ModelSim which will simulate VHDL. I believe that Xilinx does the same. However, it is a windows only tool.[/q] Really? I am runing ModelSim Altera Starter Edition under native linux. Altera provides a free version of ModelSim which will simulate VHDL. I believe that Xilinx does the same. However, it is a windows only tool. Really? I am runing ModelSim Altera Starter Edition under native linux.

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