Hi, all

Let's talk about register definition in this thread.

I think the following registers should be defined in the specification:

1) source yuv raw data address of the frame to be encoded;
2) reconstructed yuv address of the frame to be encoded;
3) start address of bit stream buffer;
4) size of bit stream buffer;
5) current offset of bit stream buffer;
6) sps register;
7) pps register;
8) slice header register;
9) slice partition register (start mb_idx and end mb_idx);
10) address of forward/backward reference frames of the current frame;
11) configuration register for intra prediction (modes supported, etc.);
12) configuration register for inter prediction (widht and heigth of search window for motion estimation);
13) Lagrangian Factor for intra and inter mode decision;
14) register to start hardware encoder (encode sps/pps/sliceheader/slice_data);
15) status register (hardware busy, etc.)
16) statistical information returned by hardware to do rate control;
17) interrupt configure register
18) interrupt status register ( encode sps/pps/sliceheader/slice_data done, bit stream buffer full, etc.)
19)...

please comment.

Best Regards,

Jack.

Hi Jack, Could you please explain these register?

I suggest:
register for start-address of current buffer for encoded data in the memory.
register for current location in current buffer.
register for next buffer for encoded data in the memory.
register for FW to "tell" HW that current slice for encoding is ready ("Go" register).
...