Dear all,

I am working at a university and we are currently working towards a multicore demonstrator FPGA platform using the OpenRisc core.

Did anybody of you do work on this? Is anybody interested in collarborating on this?

I propose to work on a specification of an "OpenRisc MP" with the necessary extensions of the core. Further extensions, such as cache coherency, Linux-SMP extensions etc. also need to be discussed.

For now, we have implemented a CPU-ID register, that is SPR_SYS register 9, to allow different stacks in the same memory etc.

For now we are: Ravi, that also recently used this forum, and me.

I very much appreciate your feedback.

Bye,
Stefan

I suggest you look up the work of Theo Kluter, a PhD student at the EPFL in Switzerland. It's been more than a year since I last saw his work (he's probably finished by now), but at the time he had an OR1000 SoC with up to 4 CPUs, including cache coherence and an improved cache architecture. You can probably find him, his work, and/or his thesis from the web page of the processor architecture lab, http://lap.epfl.ch.