Hi everyone,
I wanted to run the RTL simulation of orpsocv2 by NC-Verilog. However, I had some problems when running the simulation. The error messages seem to be some problems with the RTL codes, but I don't know how to modify. Also, I had found the parameter $(MAKE)never defined in sim/Makefile. Can someone help me how to solve these problems?

Thanks very much.


The error messages are showing below:

ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../bench/verilog" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../bench/verilog/vpi/verilog" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../backend" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/uart16550" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/ethernet" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/fpu" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/or1k_startup" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/spi_ctrl" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/or1k_top" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/or1200r2" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/tap" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/smii" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/debug_if" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/wb_sdram_ctrl" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/ram_wb" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/wb_conbus" given but not used.
orpsoc_top dut
|
ncelab: *E,CUVMUR (/home/users2008/bswu/openRISC/orpsocv2/bench/verilog/orpsoc_testbench.v,129|16): instance 'orpsoc_testbench.dut' of design unit 'orpsoc_top' is unresolved in 'worklib.orpsoc_testbench:v'.
or1200_monitor monitor();
|
ncelab: *E,CUVMUR (/home/users2008/bswu/openRISC/orpsocv2/bench/verilog/orpsoc_testbench.v,327|24): instance 'orpsoc_testbench.monitor' of design unit 'or1200_monitor' is unresolved in 'worklib.orpsoc_testbench:v'.
ncverilog: *E,ELBERR: Error during elaboration (status 1), exiting.
TOOL: ncverilog 08.10-s007: Exiting on Mar 02, 2010 at 23:42:14 CST (total: 00:00:00)

You don't have to define that, make automatically knows what it means.


Were there any other errors during compilation? I don't have access to NCSim right now, so can't test this. It looks like maybe the top level file of ORPSoC's RTL and the OR1200 monitor aren't getting compiled in the right place, or even at all.

Did you see any other warnings earlier on in compilation?

The log file is attached.
There were warnings that the verilog files in all dictionaries can't be used, but I found that the dictionaries with the code "+incdir+" and "-y" of the generated script were not consistent.

make[1]: Entering directory `/home/users2008/bswu/openRISC/orpsocv2/sw/support'
make[1]: Nothing to be done for `all'.
make[1]: Leaving directory `/home/users2008/bswu/openRISC/orpsocv2/sw/support'
make[1]: Entering directory `/home/users2008/bswu/openRISC/orpsocv2/sw/utils'
make[1]: Nothing to be done for `all'.
make[1]: Leaving directory `/home/users2008/bswu/openRISC/orpsocv2/sw/utils'

Beginning loop that will complete the following tests: basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc

################################################################################

\t#### Current test: basic-nocache ####

\t#### Compiling software ####

make[1]: Entering directory `/home/users2008/bswu/openRISC/orpsocv2/sw/basic'
or32-elf-gcc -T ../support/orp.ld basic.o ../support/reset-nocache.o -o basic-nocache.or32 ../support/except.o ../support/libsupport.a
or32-elf-objcopy -O binary basic-nocache.or32 basic-nocache.bin
../utils/bin2hex basic-nocache.bin 1 -size_word > basic-nocache-twobyte-sizefirst.hex
../utils/bin2vmem basic-nocache.bin > basic-nocache.vmem
make[1]: Leaving directory `/home/users2008/bswu/openRISC/orpsocv2/sw/basic'

\t#### Compiling RTL ####


\t#### Beginning simulation ####
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../bench/verilog" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../bench/verilog/vpi/verilog" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../backend" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/uart16550" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/ethernet" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/fpu" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/or1k_startup" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/spi_ctrl" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/or1k_top" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/or1200r2" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/tap" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/smii" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/debug_if" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/wb_sdram_ctrl" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/ram_wb" given but not used.
ncvlog: *W,LIBNOU: Library "/home/users2008/bswu/openRISC/orpsocv2/sim/run/../../rtl/verilog/components/wb_conbus" given but not used.
wb_conbus
|
ncelab: *E,CUVMUR (/home/users2008/bswu/openRISC/orpsocv2/rtl/verilog/orpsoc_top.v,255|11): instance 'orpsoc_testbench.dut.wb_conbus' of design unit 'wb_conbus_top' is unresolved in 'worklib.orpsoc_top:v'.
or1200_monitor monitor();
|
ncelab: *E,CUVMUR (/home/users2008/bswu/openRISC/orpsocv2/bench/verilog/orpsoc_testbench.v,327|24): instance 'orpsoc_testbench.monitor' of design unit 'or1200_monitor' is unresolved in 'worklib.orpsoc_testbench:v'.
ncverilog: *E,ELBERR: Error during elaboration (status 1), exiting.

The monitor showed the messages.

I think the verilog file extension is not being assumed by ncverilog when compiling.

The command that is needed to be added to ncverilog when compiling is +libext+.v

It's specified in the compile script for modelsim, but not for icarus. Change the compile script to modelsim's one by changing the SIM_COMMANDFILE variable when using ncverilog in the makefile (sim/bin/Makefile) by changing this:

ifeq ($(SIMULATOR), $(NCVERILOG))
# NCVerilog uses same command file as Icarus
SIM_COMMANDFILE=$(ICARUS_COMMAND_FILE)
endif


to this:

ifeq ($(SIMULATOR), $(NCVERILOG))
# NCVerilog uses same command file as Icarus
SIM_COMMANDFILE=$(MGC_COMMAND_FILE)
endif


Let me know if that fixes it and I will update the files in the repository.

Thanks.
I could run the simulation by ncverilog but the Makefile needed a modification.

#Change this line
GENERATED_COMMANDFILE=$(SIM_COMMANDFILE).generated
#to
GENERATED_COMMANDFILE=$(MGC_COMMAND_FILE).generated

I didn't know why I needed to modify this line, but simulation would fail without modification.

I had ran the ncsim, but the simulation results were failed.

Warning! $readmem error: invalid syntax in file "sram.vmem" at line 1025
File: /home/users2008/bswu/openRISC/orpsocv2/rtl/verilog/components/ram_wb/ram_wb_sc_sw.v, line = 36, pos = 26
Scope: orpsoc_top.ram_wb0.ram0
Time: 0 FS + 0

ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
TOOL: ncverilog 08.10-s007: Exiting on Mar 04, 2010 at 00:30:44 CST (total: 00:00:05)

Which test is that for, basic-nocache, the first very one of the set?

The log files were attached. The simulations all failed.
I just ran the rtl-tests.