Is OR1200 data and instruction Wishbone interface B3 compatible? Because after I send first byte and assert ACK, than OR deassert STB, but according to WB B3 spec. should be STB and CYC asserted during whole cycle. I tried to continue burst anyway, but it seems not working.

Or is there any memory core, that supports bursts and is compatible with OR1200?

Thanks for help

They should be. But you have to configure them to be B3 by uncommenting line 439 of or1200_defines.v "//`define OR1200_WB_B3". This is standardly not set. Still be sure that OR1200_NO_BURSTS is not defined, normally it wouldn't be.



Well, it is possible that the data or instruction interface just want to receive one single word, so you have to stop nevertheless. If you are using neither data nor instruction caches, it is very probable that the CPU will never assign Wishbone burst transfers. This is standardly off, lines 332 and 337 of "or1200_defines.v" switch them off, you can comment them out to have cache implemented.

In order to tell if the transfer is a burst transfer, will be finished or is a classical one, you have to be aware of the signals bte and cti, specially of cti. Signal cti will tell you if the transfer will be 1) classic, 2) constant address burst or 3) incrementing burst (or end-of-burst). Bte then is able to set limits on an incrementing burst transfer by applying a 4, 8 or 16 module operation on the incrementing address so data will be overwritten after that amount of transfered data. Take a closer look at http://opencores.org/downloads/wbspec_b3.pdf , pages 73-86. Moreover from what I can read on "or1200_iwb_biu.v" and "or1200_wb_biu.v" max transfer length on a burst transaction would be 4.

Furthermore the interconnect you use has to include/forward the bte and cti signals, which is not the case from the wb_conmax and wb_conbus interconnets (as far as I can tell). You could though, simply add them to these interconnects and it should work flawlessly.



From some standard I know, none is compatible, but I didn't look for it either.

Best regards,
Raul

I have done some simulation and it looks that there must be a "blank" cycle between 1st word and the others. So you should send 1st word, than wait one cycle and than send 2nd 3rd and 4th word.

For instruction bus this works OK, but for data not. So for data bus you have to left "blank cycle between each word.

Hi Iguaner,



From my analysis of the Verilog files related to the two interfaces:
instruction interface: or1200_iwb_biu.v
data interface: or1200_wb_biu.v

Even with all the configuration described on my previous post, the negation of stb upon acknowledgment of slave you describe will always happen. Actually even cyc will be negated too, is that so?

This behaviors are described on:
or1200_iwb_biu.v, line 431:
wb_stb_o or1200_wb_biu.v, line 393:
wb_stb_o
As you can see, the assertion of wb_ack_i (which is standardly unregistered) will inevitably lead to a registered negation of stb and the same behavior goes for wb_cyc too.

It seems B3 has not been thoroughly implemented on or1200, it has been adapted from an older signal composition of cab signals, I don't know anymore of.



To understand how the or1200 implemented master Wishbone interfaces couple with your attempt to force inputting data, the interface used to forward this data to the caches implemented inside of the or1200 has to be taken into account.

It seems to be another Wishbone one, but I'm not sure about its configuration. Directly from the wb_dat_i signal I couldn't derive any issues, maybe it is related to the internal acknowledgement of the forwarded data, the abort signal, addressing or even something else, it really has to be analyzed yet.

Anyhow I already wanted to give some response to your question. Maybe you can find a solution yourself too.

Best regards,
Raul