I used the Artisan Single-Port SRAM for synthesis.
There is an error in the or1200_spram_2048x32_bw.v because of a width mismatch of input "we", but the write enable input of SRAM is only one bit. I didn't know how to modify the verilog code. If someone can help me.
Thanks.

input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input [3:0] we; // Write enable input
input oe; // Output enable input
input [10:0] addr; // address bus inputs
input [31:0] di; // input data bus
output [31:0] doq; // output data bus


`ifdef UNUSED
art_hssp_2048x32_bw artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x32_bw_bist artisan_ssp(
`else
art_hssp_2048x32_bw artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);

Isn't that an ASIC memory library? Are you actually synthesising for an ASIC? If not I would stick with one of the memory techs that will infer an FPGA block memory if synthesised for FPGA. When sythesising for an ASIC you would have a fairly good idea of target memories and probably do up your own technology files for the OR1200.

You could bitwise-OR the we signal together and put it on the active low write enable port like this:

Maybe that's not write, maybe you need to declare a wire and assign that to it, like this:

and then put that on the we port.

Hi Binshu,



try adding between artisan_ssp and the fist name on the 3 corresponding lines the following: #(32, 2048, 11)

Like this:
`ifdef UNUSED
art_hssp_2048x32_bw #(32, 2048, 11) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x32_bw_bist #(32, 2048, 11) artisan_ssp(
`else
art_hssp_2048x32_bw #(32, 2048, 11) artisan_ssp(

I traced back the driving signal of that write enable and it must be 4 lines. The driving signal is at the end the dcpu_sel_o signal of or1200_lsu.v, which only asserts the according write enable bits to write byte-wise (8 bits) to a 32-bit memory.

If a firmware tries to read from unaligned memory spaces, not multiple of 4 at the end. 0x0001-0x0003 (not 0x0000, 0x0004, 0x0008, 0x000C), the CPU will end up asserting write enables which are not exactly 4'b1111 but 4'b0001 and so on. Also if they are aligned but the loaded variable is declared as less than 32 bits this would also happen.

In other words this is necessary. If the proposed solution doesn't work, some other solution has to be found out. It would also be possible to instantiate 4x 8-bit wide artisan memories and connect them to be 32 and so have different write enables. A template for the 8 bit wide artisan memory can be found on "or1200_spram_2048x8.v". And a guideline on how to connect them together can be found on the "or1200_spram_2048x32_bw.v" itself, for the RAMB16_S9 instantiations, lines 552-607.

So, ask again if the proposed solution doesn't work and I will clarify how to try the second option.

Good luck,
Raul