Hi,

I'm looking for a core to replace an external PPC405EX in Xilinx Virtex7.

FPGA pins are the limiting factor rather than maximum horsepower.

I've been looking at Von Neumann MIPS offerings as a single exteral bus can be used for both program and data reducing pin count.

Is it possible to use the OpenRISC in this way?

Thanks,

John

I believe so.

It's not already done, but you could simply write a small arbiter that would sit between the current processor bus outputs and your custom bus, thus reducing the pin count to whatever you like.

The OR1200 is mainly implemented in modified hardvard architecture form, so reducing the actual I/O for instruction and data busses shouldn't change how it operates. Ie. you could keep all caches, MMUs, etc in there.

Just tie all the buses (instruction/data) together into a single external bus.
Write a simple bus controller (finite state machine) that controls when which of the two buses (instruction/data) accesses the external bus.

If the caches do a good job they should hide most of the external accesses. When external accesses are required they should be in the form of a (cache-line) burst.
When both instruction and data buses need to access the external bus I suggest you give the data bus a higher priority, because programs typically wait for data (not for instructions). And even then ... what's the point of loading new instructions if the old ones are waiting for data??

Small note: that latest remark is handled by an out-of-order CPU. The current implementation of OpenRisc is not OOO capable and hence giving data higher priority makes sense.

Cheers,
Richard

Good point Richard, definitely give data bus the priority in any instruction/data bus multiplexer module.

Thanks for the ideas guys..

I've just stumbled across the ORPSoCv2 which I think will be a better starting point.

If anyone has ported this to the ML605 Xilinx Dev Kit please get in touch.

John