Hi, I'm trying to synthesise the OrpSoC for a Sakura-G board (Spartan-6 based). I create a project with ISE starting form the ucf file found on the reference page of the Sakura board and I added the orpsoc files. If I try to synthesise each single sub-modules instantiated by orpsoc_top (for example or1200_top.v), the synthesis process completes, but if I try to synthesise the top module orpsoc_top.v, the synthesis process doesn't finish and saturate the RAM of my laptop (16 GB). I get no errors during synthesis process but a lot of warnings; the last message shown in the console out is: "Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimed during the optimization process." during the low level synthesis. Any idea about that? Thanks Luca

The top level adds in a large amount of ram and rom. You could be running out of fpga resources. Try trimming them down to very small sizes and rerunning.


John Eaton

Hi, thank you for the answer. The problem is exactly that. Now I'm trying to use the Atlys orpsoc_top module as top of the project. It uses the Mig and a DDR controller. The problem now is how to initialize the memory! I can't understand how to write my .bin or .vmem file obtained by compiling the C source code I want to simulate.

Someone can help me?

Thanks

Luca