hello,everyone,I want to konw that which tools can make my own
verilog module to ip?
please tell me ,thank you

Hi,

well, as far as OpenCores are concerned it is already an IP core. That is because here all IP cores are delivered as a Verilog Project for to hold the source open.

However there are guidelines people follow to help other users using your core. These are described here: www.opencores.org/downloads/opencores_coding_guidelines.pdf .

I hope it helps you, best regards,
Raul