Hi everyone,

I need to make RX and TX with clock generator for UART SPORT (serial port), and it has to be in Verilog.
Maybe someone has a written code, or some parts of it?

Thanks

Hello,
unfortunately I'm writing in VHDL only. But on the Projects site you can find a lot of UART and USART and I'm sure you will find what you need.

If you're still looking, I just published a Verilog UART project here ( http://opencores.org/project,osdvu ). Would be keen to have someone else do a test drive and provide feedback.