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Help in verilog ...
by capricorn_umair on Jul 27, 2010
capricorn_umair
Posts: 1
Joined: Jul 14, 2010
Last seen: Sep 17, 2010
I have given a task of writing a verilog code for moving the stepper motor for desired number of steps in either clock wise or CCW direction . i have written the following code but when i simulate it using model sim , it shows high impedance values for all the ports ... the code is given below ...

================================================== ====

// PROGRAM BLOCK
module stepper(out ,n_steps, dir_CW);
output reg [3:0]out;
input [7:0]n_steps;
input dir_CW;
integer i;

initial
begin
i out end

always @(n_steps or dir_CW)
begin
if (dir_CW ==0)
begin
while(i>=4)
begin

#2 out = 4'b1001;
#2 out = 4'b1010;
#2 out = 4'b0101;
#2 out = 4'b0110;
i = i - 4;
end
if (i==3)
begin

#2 out = 4'b1001;
#2 out = 4'b1010;
#2 out = 4'b0101;

end


else if (i==2)
begin

#2 out = 4'b1001;
#2 out = 4'b1010;

end


else if (i==1)
begin

#2 out = 4'b1001;

end
else;
end


else
begin
while(i>=4)
begin

#2 out = 4'b0110;
#2 out = 4'b0101;
#2 out = 4'b1010;
#2 out = 4'b1001;
i = i - 4;
end
if (i==3)
begin

#2 out = 4'b0110;
#2 out = 4'b0101;
#2 out = 4'b1010;

end


else if (i==2)
begin

#2 out = 4'b0110;
#2 out = 4'b0101;

end


else if (i==1)
begin

#2 out = 4'b0110;

end
else;
end

end
endmodule

// TESTING BLOCK
module test;
reg [7:0]N_STEPS;
reg DIR_CW;
wire [3:0]OUT;

stepper stpr(OUT, N_STEPS, DIR_CW);

initial
begin
$display("no of steps = %b, CW direction = %b, coils output = %b\n", N_STEPS,DIR_CW,OUT);
end

initial
begin
N_STEPS= 8'b0001_0000; DIR_CW= 1'b0;
// #100 N_STEPS= 8'd80; DIR_CW= 1'b1;
end
endmodule


================================================== =====

please anybody help me out in correcting this code if the logic gets wrong as i m new to verilog ...

Regards
Umair
RE: Help in verilog ...
by narendra_27 on Jul 27, 2010
narendra_27
Posts: 2
Joined: Aug 19, 2009
Last seen: Jan 20, 2012
I am not addressing ur current problem.
but the code u have written is ok for simulation purpose.
The delays u have mention will be ignored in systhesis, aswell as while running with
FPGA.I think the code u have written wont work in reality.

My suggestion make it a ring counter with initializing with 1010 r whtever u want to be cyclic.
run that counter with specified clock speed. For that u need to use system(FPGA) clock and divided that clock for the speed u want and apply that clock to ur ring counter that will work out ur goal.

I tried this in my robotics experiment........... u may get issuses related to driving stpper motor with FPGA driving capabilities too..........
RE: Help in verilog ...
by narendra_27 on Jul 27, 2010
narendra_27
Posts: 2
Joined: Aug 19, 2009
Last seen: Jan 20, 2012
did u understnad what i said........
no use no use 1/1 no use no use
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