Hello there. I am currently working on designing a single-cycle MIPS processor. However, it hasn't been an easy task. Even tho, simulation may work well for different functional blocks, it seems synthesizer is removing logic it thinks is unused but it is actually essential. To address these issues, I began testing diff. sections of the processor individually, having still the same result.

For example, the files I attach describe a simple RAM with words of 1 byte, which has a 32 bits input, as well as an output of the same width, with Memory read and write enables. This memory is filled by a module called fill_mem which proceed on doing so on negedge clock. Once this is done in some cycles it will raise a flag (assert a signal) which will indicate the RAM is filled with data that can be now accessed, then the module com_out takes RAM output data to FPGA I/O pins when a signal tells it to do so (ready signal).

As I said, this works pretty well on simulation, but upon synthesis, it shows these warning messages:


[Synth 8-3332] Sequential element (FM1/out_reg[31]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[27]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[26]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[25]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[24]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[23]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (FM1/out_reg[20]) is unused and will be removed from module DATATEST....

[Synth 8-3332] Sequential element (FM1/out_reg[8]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[0][0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[2][0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[4][0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[6][0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[8][0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[10][0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[12][0]) is unused and will be removed from module DATATEST.
[Synth 8-3332] Sequential element (DM1/MEM_reg[14][0]) is unused and will be removed from module DATATEST.,..

[Synth 8-3332] Sequential element (CM1/address_reg[0]) is unused and will be removed from module DATATEST....

[Synth 8-3917] design DATATEST has port led[1] driven by constant 0


And frankly, I am not sure of how to solve it. Any help would be appreciated. I will attach the files. Someone told me I am working in a very sequential way. I know hardware may work in a parallel way, but since I am using a clock signal, and other control signals, it most likely won't, since this actually for a processor in the end.

Thanks in advance.

To know how to build a RAM for an FPGA, and particularly for a Xilinx FPGA, you'll want to follow the coding guidelines that Xilinx provides in their "HDL Coding Practices to Accelerate Design Performance".

Other architectures have similar coding guidances, but I don't have any of those handy.

Let me know if you need more help,

Dan