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Message
From: Mahmud Galela <mgalela@v...>
Date: Mon, 19 Feb 2001 17:26:50 +0700 (JAVT)
Subject: RE: [ethmac] rx_ethmac
On Tue, 13 Feb 2001, Illan Glasner wrote:
> 13-Feb-01
>
> Mahmud Hi,
>
> Just few more comment's :
>
> 1.
> If I may suggest instead of the long long stimulus file that have :
>
> "
> ...
> run 40
> force rx_data 1011 0
> run 40
> force rx_data 1111 0
> run 40
> force rx_data 0101 0
> run 40
> force rx_data 0011 0
> ...
> "
>
> etc it would be better to use the random function and a loop with random
> size this will take only few lines as well as the tester will be much
> more robust as it test every run a new pattern.
>
> easiyl you can than add change in preamable size wchihc also will be
> random and good/bad sfd random and so on so with few random line you get
> a much more verification cover.
>
> oh and don't forget of course to change the seed before each run.
>
oh thanks, i'll try.
The second frame of present stimulus file is the same
as one used in mike's design...
>
> 2.
> In the crc module I notice you used function and was wonder if you took
> them from the http://www.easics.be/webtools/crctool if so it would be
> appropriate if you add a comment in your code that it was taken from
> there.
> on the other hand if it is all from your head than forget what I write.
>
I derivated my self with some clues from
www.cypress.com/pub/appnotes/crc.pdf and compared with generated one from
www.easics.be/webtools/crctool There are differences in the sequence of
incoming data.
If there is someone who want to know the shifting table to determine the
functions, i can send by email. By the way thanks to the maintainer of
easics.be because i can imagine the program which is used to derivate
those codes.
>
>
> 5.
> Why do you have in the sm so many hold and wait states ?
>
> I belive that from idle to start you go when rxdv=1 than when sdf=1 you
> go to start.
> and in all states if rxdv=0 you go to end where you either report the
> result or error depend on you. and next clock return to idle or maybe
> you can combine end and idle depend on your coding.
i get some difficulties to synchronize all of subblocks work...
after rx_dv non-active...there's
- still 2 nibbles data in buffer that need 2 clocks to send all to FCS
checker, and deactivate data_en.
- FCS checker needs 1 clock to give the checking result. (crc_ok or
not_ok)
>
> have a nice day
>
> Illan
>
thanks,
Mahmud
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