Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: "Igor Mohor (uni-mb)" <igor.mohor@u...>
Date: Wed, 7 Mar 2001 19:09:25 +0100
Subject: [ethmac] fifo_synch.v

Hi, Guys.

I'm working on MII and MAC Control Module.
I see some problems in the fifo_synch.v. Data is coming from the host and is
synchronized to the host clock. To synchronize it to the clk, you need two
clocks and not just one (metastability).

The file should look:

always @(posedge clk)
  if (transmit_enable)
    begin
      temp_txd <= data;
      temp_tx_en <= 1'b1;
      temp_tx_er <= transmit_error;
    end
  else
    begin
      temp_txd <= 4'h0;
      temp_tx_en <= 1'b0;
      temp_tx_er <= 1'b0;
    end

always @(posedge clk)
  if (transmit_enable)
    begin
      txd <= temp_txd;
      tx_en <= temp_tx_en;
      tx_er <= temp_tx_er;
    end
  else
    begin
      txd <= 4'h0;
      tx_en <= 1'b0;
      tx_er <= 1'b0;
    end

Let me know if I am wrong.

PS.
Is somebody else working on the MII and MAC Control Module?


Regards,
	Igor

Follow up	Author
Re: [ethmac] fifo_synch.v	Vikas Mishra