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    Navigation: All forums > Ethmac > Message List > Message Post

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    From: "Bert Douglas" <bertd@i...>
    Date: Wed, 18 Apr 2001 09:27:22 -0500
    Subject: Re: [ethmac] about signal setup time
    Top

    It seems to me that there is 1 whole cycle of setup time.
     
    ----- Original Message -----
    From: <zixim@2...>
    Sent: Wednesday, April 18, 2001 6:40 AM
    Subject: [ethmac] about signal setup time

    Hi,

    In the verilog code of this ethernet ip core, I found that the
    data of txd[3:0] vary at the positive edge of tx_clk. Then, there
    is no setup time for the data. Why?


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    [ethmac] about signal setup timeZixim
     
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