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Message
From: "Tal Weiss" <tal@c...>
Date: Wed, 27 Feb 2002 15:20:27 +0200
Subject: RE: [ethmac] Ethernet status
Hi Benjamin Heyne,
How many CLBs did the core end up taking? (W/O the Shark IF, if possible).
Thanks,
Tal.
-----Original Message-----
From: owner-ethmac@o... [mailto:owner-ethmac@o...]On
Behalf Of Benjamin Heyne
Sent: Wednesday, February 27, 2002 2:23 PM
To: ethmac@o...
Subject: Re: [ethmac] Ethernet status
Hi !
I have implemented the core (MIIM, Rx and Tx) for an Ethernet measurement
tool in a Xilinx Spartan (XCS30XL). I am not using the Wishbone interface -
The core is using a SHARC DSP LinkPort to connect to the world. So I have
not tested the Wishbone part of the core.
I have ported the parts I am using for my design to VHDL and modified esp.
the Rx and Tx modules to support the LinkPort interface of the SHARC and
certain other features needed for measurement. The basic Rx/Tx routines are
untouched. In my implementation the DSP has to code/decode the MAC adresses,
so I have also removed this parts from the core.
To test the design in the "Real World" a PCB containing some LinkPorts and a
MII Port was made.
As far as I can say the core is working - although I have not yet tested it
in Full Duplex mode.
It was neccessary for the TX MII signals to change on the falling edge of
TxC - otherwise the Transceiver sometimes got the wrong data.
If someone is interested in this design I will place it on an public
download site.
==============================================================
Lehrstuhl fuer Kommunikationstechnik,Universitaet Dortmund
Otto-Hahn-Strasse 4, 44227 Dortmund, Germany
Tel: ++49-231-755-3195, Fax: ++49-231-755-3196
www.kt.e-technik.uni-dortmund.de, Raum P1-03-212
----- Original Message -----
From: "Igor Mohor" <igorm@o...>
To: "Ethmac@Opencores. Org" <ethmac@o...>
Sent: Tuesday, February 26, 2002 11:10 AM
Subject: [ethmac] Ethernet status
> Hi, Guys,
>
> these days I'm putting ethernet to the actual hardware. FPGA
> (VirtexE 1600) is going to contain the following Opencores
> IP cores:
> - Ethernet MAC
> - UART (already tested in HW)
> - RISC (already tested in HW)
> - PS2 (already tested in HW)
> - Development (debug) interface (already tested in HW)
> - Memory Controller
>
> Simulation of the whole design is already working great.
>
> Next thing that needs to be done is making ethernet core
> more popular and worth of trust.
> For this reason a good testing environment is a must. I tested
> the ethernet core on all module levels, however I don't have a
> good testing environment. I'm talking about something that people
> can take, run and get a good proof that core is really working.
>
> I know what needs to be tested. My question is if somebody already
> built an environment that can share or something like that that's
> worth working on it.
>
> Regards,
> Igor
>
>
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