LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Find Resources
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Ethmac > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Thoota Venkata <va_thoota@y...>
    Date: Mon, 8 Apr 2002 14:04:43 +0100 (BST)
    Subject: [ethmac] Synthesized Netlist for ethernetMAc 10/100 code
    Top

    Hi there,
    
    Let me introduce myself, I am a Layout design trainee
    working on Avanti tools. I have come across your
    EthernetMac 10/100 code at opencore.org and was very
    interesting. I want to try making the layout for your
    code using avanti tools targetted to 0.25 micron
    passport library.
    
    In this regard it would be of great help if you can
    forward the following.
    
    1. Synthesized gate level netlist targeted to the
    above library specified.
    2. The timing constraint file for carrying out timing
    verification on layout.
    
    or Please arrange to send the design constraint file
    so that I can synthesize on design compiler.
    
    Thnaking your for providing very good core on the web.
    
    Best Regards,
    
    Venkata Apparao.
    
    ________________________________________________________________________
    For live cricket scores download  Yahoo! Score Tracker
     at: http://in.sports.yahoo.com/cricket/tracker.shtml
    
    
    

    Follow upAuthor
    RE: [ethmac] Synthesized Netlist for ethernetMAc 10/100 codeIgor Mohor

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.