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Message
From: brecht@c...
Date: Tue, 30 Apr 2002 12:19:26 +0200
Subject: Re: RE: [ethmac] CRC
Hi Illan! Hi all!
As a typical CRC-newbie...do I understand this right or not(?):
I take the CRC-function from easics, fill the register with ffffffff as
the first step.
Afterwards I run it (in VHDL in a clk'event-process doing sth like CRC
<= NewCRC) and as the last step I fill it compeletely with zeros (like
other CRCs work).
To use the CRC in my ethernet core I will have to invert and reflect it.
After all I will pass it in nibbles starting with the highest nibble
(bit 31 downto 28) to the PHY.
I tried and tried but failed.
I am sorry I couldn't figure it out of your open cores model as I am
really new in this and have never spent time on verilog...
Can you or anybody help?
I appreciate your help!
Have a jolly good day!
Christian
germany
Illan Glasner <iglasner@z...> schrieb am 30.04.2002,
02:35:57:
>
> Waman Hi,
>
> no need to design any crc module simple go to
>
> http://www.easics.be/webtools/crctool
>
> enter the width etc and you will get the module with no effort and 0 time.
>
> have a nice day
>
> Illan
>
>
> -----Original Message-----
> From: waman mainkar [mailto:waman_m@y...]
> Sent: Friday, April 26, 2002 10:51 PM
> To: ethmac@o...
> Subject: [ethmac] CRC
>
>
> Hi,
> i am designing ethmac for gigabit ethernet....
> and now designing crc module but, i couldn't exactly
> understood how ex-or and shift happens.
>
> so if you can explain to me with example, i'll highly
> appriciate that.
>
> Thanks,
>
> Waman.
>
>
>
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