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Message
From: Javier_castillo_villar@y...
Date: Fri, 17 May 2002 16:09:18 +0200
Subject: RE: [ethmac] Does anyone has source code of asyn fifo?
Hi:
Itīs much better to use a coregen or megawizard fifo for your design.
If you describe a fifo in vhdl and then you sinthetize it, you use a CLB
for each bit you want to store, so if you are using a 16x8 fifo you are
using at least Ą128 CLB!. If you use a core generator program you are
using internal resources of the FPGA and special configurations of the
CLBs. In this case you can easily store 16 bits or more in each CLB.
You MUST NOT implement a memory in VHDL with a array, you have to
generate a memory with coregen or megawizard or a program like this.
Your FPGA suplier offer it for free.
I am agree with you when you say an eng must know how to make a
fifo but itīs not a good idea to sinthetize it.
Nice day
----- Original Message -----
From: "Illan Glasner" <iglasner@z... >
To: <ethmac@o... >
Date: Thu, 16 May 2002 19:32:05 -0700
Subject: RE: [ethmac] Does anyone has source code of asyn fifo?
>
>
>
> Hi,
>
> Two small comment :
>
> 1.
>
> Notice that using Coregen or Megawizard the memorey usage of your
> Unix machine (and I assume the same with PC but can't say for sure
> as I use only Unix) is much more than simple use the "pure" memorey
> and write your own fifo/mem-ctrl etc etc.
>
> as for the timing it is just as good.
>
> 2.
> BUT even more important why not try and do it yourself ?
>
> after all you chose to be an Eng so give it a try fight with this
> until you get it.
>
> otherwise you become just as any other who know how to do what
the
> Megawizard/Coregen can do, maybe also use IP core ...
>
> Yes if you want to make 8/10 for sure use it as otherwise writing
> the table by your own you will no doubt make dozen's of typo but
> fifo are something very elementry and assuming you are "new" to
> this most likely when you will try to get a new job (or first job)
> you will be asked about such thing and I belive an answer like "I
> press the megawizard or the coregen" will not be too impressing.
>
> have a nice day
>
> Illan
>
>
> -----Original Message-----
> From: Javier_Castillo_Villar@y...
>
> [/cgi-bin/post.cgi?cmd=new&to=Javier_Castillo_Villar%20at%
20yahoo%20dot%20es&msg=/ml-archive/ethmac/msg00030.shtml]
> Sent: Thursday, May 16, 2002 9:54 AM
> To: ethmac@o...
> Subject: Re: [ethmac] Does anyone has source code of asyn fifo?
>
>
> If you are using a xilinx fpga use coregen program to generate
> it, if
> you are using a altera fpga use megawizard program. Both are free
> and
> they are suplied with the other xilinx or altera tools
>
> ----- Original Message -----
> From: zou.yixin@z...
> To: ethmac@o...
> Date: Mon, 13 May 2002 09:48:29 +0800
> Subject: [ethmac] Does anyone has source code of asyn fifo?
>
> >
> >
> >
> > Hi,
> > Does anyone has the source code of asynchronous fifo or
> somewhere
> > to find
> > it?
> > Thanks.
> > yxzhou
> >
>
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