OpenCores
OpenCores and general hardware news

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ZTEX releases new Artix 7 FPGA Board with USB and DDR3 SDRAM
posted by Stefan, Ziegenbalg on 10-Apr-2014
ZTEX releases USB-FPGA Modules 2.13 with Artix 7 XC7A35T to XC7A100T FPGA, USB 2.0 controller, 256 MByte DDR3 SDRAM and on-board voltage regulators.
ZTEX releases a FPGA Board with largest Artix 7 FPGA
posted by Stefan, Ziegenbalg on 25-Nov-2013
ZTEX releases USB-FPGA Module 2.16 with Artix 7 XC7A200T FPGA, USB 2.0 Controller, on-board voltage regulators and many I/O's.
Abstract — A IDCT architecture is designed for

multistandard inverse transform. The proposed

architecture is used in multistandard decoder

of MPEG-2, MPEG-4 ASP, H.264/AVC and

VC-1. Two circuits share strategies, factor

share (FS) and adder share (AS), are applied

to the inverse transform architecture for saving

its circuit resource. Finally, the architecture is

extended as 2-D using registers as row to column

decomposition

Keywords — Circuit share, high-definition

video, multistandard inverse transform, multi-

standard, IDCT, reconfigurable architecture
open hardware survey
posted by Andres, Cicuttin on 21-May-2012
This is an invitation to participate to a survey on an open hardware initiative for sciintific purposes in line with UNESCO mission. The results will be share with all participants and will be used to raise awarnes of new ways of open collaboration and project sustainability in line with opencores' spirit.
Many thanks,
Andres Cicuttin,
Technical Assistant
ICTP (UNESCO-IAEA)
The Libre Software Meeting (LSM) is an annual event on free software taking place in july in France since 2000. The LSM meeting is organized this year in Geneva, Switzerland from 7th to 12th July. Amongst several tracks, the Libre Software Meeting will feature an « Embedded Systems and Open Hardware » track, for which the call for presentations has been released recently.
Migen, a Python toolbox for building complex digital hardware
posted by Sebastien, Bourdeauducq on 27-Jan-2012
The Milkymist project has started developing a new high level tool for the synthesis of complex digital systems.
DMAP, a company focused on high reliability semiconductor applications and producing DO-254 compliant IP, has made available to the market PCI Express and Ethernet (Gigabit, 10G) IP for DO-254 applications that has been verified using SystemVerilog and Assertion Based Verification (ABV) in an OVM environment.
The NEW OpenRISC FPGA development board is now released
posted by Marcus, Erlandsson on 22-Nov-2011
The new OpenRISC-FPGA-development board is now released and it's specially designed to match OpenRISC processor SoC designs. The board supports the most common/wanted interfaces, with a small physical size and easy connections/debugging solution. We offer this powerful board as a low-cost FPGA development board, back to the community.
Sigasi Starter Edition, Forever Free
posted by Philippe, Faes on 01-Jul-2011
Sigasi launched a Starter Edition of its VHDL design environment. The starter edition will be permanently free of charge. If your project is small enough (and dozens of OpenCores projects are) you even get the full functionality of the Pro version.
New Book: 100 Power Tips for FPGA Designers
posted by evgeni, stavinov on 30-Jun-2011
Now available in paperback and e-book formats, “100 Power Tips for FPGA Designers” book is a collection of short articles on various aspects of FPGA design: synthesis, simulation, porting ASIC designs, floorplanning and timing closure, design methodologies, design optimizations, RTL coding, IP core selection, and many others.
In this article, we suggest to build on-die switched-capacitor voltage regulators to significantly reduce the power consumption of the OpenRISC SoCs while maintaining performance. We hope to gain your feedback to better understand the SoCs voltage regulators' needs.
After years of passionate and engaging development, the video synthesizer from the Milkymist project, with open source IP, is expected to go out of beta in August.
UK OSHUG to cover OpenCores and OpenRISC
posted by OpenCores, Admin on 07-Apr-2011
The next meeting of the Open Source Hardware Users Group (OSHUG) will include a talk (by me) on OpenCores and OpenRISC. The meeting on the evening of 21 April will also include an Introduction to Programmable Logic and a talk on using FPGAs for Computer Conservation.

Attendance is free and full details can be found at:
http://oshug.org/event/9
theora encoder core
posted by Vasiliy, Vasilievich on 16-Mar-2011
looking for interested for creating open theora encoder core. If you are interested e-mail me.
Neither Emacs nor VI are the most popular VHDL editor
posted by Philippe, Faes on 02-Feb-2011
In a small poll on the Sigasi website, 220 people responded to the question: Which editor do/did you use before you heard about Sigasi? We know that there is no reason to think that this test was representative of the entire VHDL development community, but the results are nevertheless interesting.
OpenCores at linux.conf.au 2011
posted by OpenCores, Admin on 26-Jan-2011
ORSoC and OpenCores will be represented at the linux.conf.au 2011 Open Day in Brisbane, Australia, on Saturday January 29.

Attending will be a member of the OpenRISC development team who will be demonstrating and discussing the platform.
All those nearby are encouraged to come along to the open day of this notable conference.

For more information see the LCA2011 site: http://lca2011.linux.org.au/programme/open_day

Also note that the original venue, as listed on the above page, is subject to change, so please double check before coming along!
The OC-team are visiting the Electronics-exhibition this week (10th-11th) in order to promote open-source hardware development.
OpenCores continues to grow with impressive speed and has now passed 100 000 registered users. Over the past three years the number of users has grown from 20 000 to today's 100 000 registered users, and the growth continues with approximately 2500 new users each month.
New AVR-compatible 8-bit RISC available, testers wanted
posted by Sebastien, Bourdeauducq on 05-Aug-2010
Need a 8-bit open source softcore with a high quality C toolchain? Please join the HW validation effort!
New job descriptions available
posted by OpenCores, Admin on 11-Mar-2010
Location in China! If you are considering the challenge of a system engineer in the telecommunications field this may be the opportunity you've been looking for. Read more here
March Newsletter
posted by OpenCores, Admin on 28-Jan-2010
The March issue of the OpenCores newsletter has been sent out and is available at the site (click here) . If you have not received the newsletter via email, please make sure to mark the checkbox in the "My Account" page. Also make sure to check you spam filter and make sure "noreply@opencores.org" is a "trusted/safe" sender. Enjoy!
Job opportunities
posted by OpenCores, Admin on 22-Jan-2010
There are 4 new job descriptions available. Read more at the Job opportunity page.
Free webinar: walking through open source hardware
posted by Philippe, Faes on 06-Jan-2010
Sigasi organizes a free webinar on Wednesday, Januari 20th, at 19:00 UTC, in which we show you how to easily inspect any open source hardware project.

An OpenRISC Update
posted by ORSoC on 30-Nov-2009
With new life being breathed into the OpenRISC project of late, it's time for an update on what has been going on, and what is to come for OpenCores' flagship project.
Free FPGA Introduction Workshop
posted by Sebastien, Bourdeauducq on 23-Nov-2009
A free FPGA introduction workshop is to be held in Paris on November 26th.
Extended project statistics
posted by OpenCores, Admin on 11-Nov-2009
The statistics of all projects at OpenCores have been extended. It is now possible to see the “profile”, in terms of expertise and experience, of the people that have downloaded a specific project.
Job Opportunity
posted by OpenCores, Admin on 05-Nov-2009
OpenCores offer a service to help companies to find the right consultant for their needs, in the fields of Technical and Electrical Engineering Services. At this page you can see all assignments we have available at the moment.
FPGA Workshop 4: Behind the Scenes
posted by Sebastien, Bourdeauducq on 21-Oct-2009
This workshop will shed light on how FPGAs work internally. Hosted near Paris, free of charge.
Free Magazine Subscriptions & Technical Document Downloads
posted by OpenCores, Admin on 21-Oct-2009
OpenCores has partnered up with Tradepub, to provide all OpenCores users with free technical magazines and other documents of interest.Click here.
Dear OpenCores community,I want to start a new project based on OpenRISC and SystemC, the goal is to set up an SoC(NoC) simulation platform for virtual prototyping, system modeling, and early software development.
Zet PC platform version 1.0 released
posted by Zeus, Gómez Marmolejo on 17-Sep-2009
Zet PC platform has reached a big milestone today, Microsoft Windows 3.0 is running on it!!
Mac OS X support for Sigasi HDT
posted by Hendrik, Eeckhaut on 07-Sep-2009
Today, Sigasi proudly announces Mac OS X support for Sigasi HDT, an Intelligent Development Environment (IDE) for VHDL.
Free FPGA Workshop near Paris, August 29th
posted by Sebastien, Bourdeauducq on 17-Jul-2009
The /tmp/lab geek collective holds an introductory workshop about FPGA SoC design.
Milkymist SoC reaches beta stage
posted by Sebastien, Bourdeauducq on 09-Jul-2009
The SoC design of Milkymist, an open hardware FPGA-based platform for video performance artists, now has all the required features to implement many video effects.
Sign up for Multimedia SoC project
posted by OpenCores, Admin on 02-Jul-2009
The new multimedia SoC project of the OpenCores community: register your talents and interest today!
50 000 registered users at OpenCores
posted by OpenCores, Admin on 02-Jul-2009
OpenCores continues to grow rapidly and we are pleased to announce that we have just passed 50,000 registered users.
Latest Newsletter from OpenCores
posted by OpenCores, Admin on 01-Jun-2009
If you didn't receive the email from OpenCores with the latest Newsletter, you can read it here.
Sigasi Public Beta: future of VHDL design
posted by Hendrik, Eeckhaut on 27-May-2009
Sigasi invites all VHDL designer for the Public Beta program for Sigasi HDT, an Intelligent Development Environment (IDE) for VHDL ( http://www.sigasi.com ).
Milkymist base SoC completed
posted by Sebastien, Bourdeauducq on 24-Jan-2009
Milkymist, an open-hardware video synthesizer, has reached an important milestone. The design for the SoC base is now completed ; the system is able to run software, interface basic peripherals, access DDRAM at high performance levels, and use a VGA framebuffer at high resolutions. Next steps are software and accelerators.
Promote your (OpenCores related) product on OpenCores.
posted by OpenCores, Admin on 11-Dec-2008
Are you one of the many companies out there who have used cores/projects from OpenCores for your product/products? Then you should take the chance to promote your product on OpenCores. Read more here
Job opportunity
posted by OpenCores, Admin on 14-Nov-2008
Two interesting consultant projects available for FPGA- and DSP engineers. OpenCores have received requests from some bigger companies within the electronic development business to find suitable engineers (as consultants) for their development projects. click here
Zet processor can boot MS-DOS 6.22 and FreeDOS 1.1 both unmodified
posted by Zeus, Gómez Marmolejo on 10-Nov-2008
The Zet processor, the x86 (IA-32) open implementation, has reached an important milestone today. It can boot MS-DOS 6.22 (the last version released) and FreeDOS 1.1 (also the latest). You can check some pictures in the project page and a simple installation guide if you have the Xilinx ML-403 board.
New ZBT SRAM Controller (WISHBONE compatible) released!
posted by Victor, Lopez Lorenzo on 30-Oct-2008
This ZBT SRAM Controller differs from others at OpenCores in that it makes the best overlap between Wishbone registered feedback burst cycles and the ZBT SRAM burst R/W cycles, so that the fastest access (a continuous burst) can be achieved.
New information:
Due to technical issues, we need postpone the "switch" to the "new" website.

Older message:
OpenCores have redesigned the website in order to make it easier add functionality. The website is expected to be down for 3-4 hours during October 29th.
The tri_mode Ethernet MAC was designed as a standalone IP for communication field. Gradually, I realized that the MAC IP core will be more popular if it can be connected to a microprocessor. Consequently, I ported the tri-mode MAC to XILINX Microblaze processor. Detail in:
http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/overview
OpenCores is pleased to announce the release of a solution aimed at lowering the technical threshold of development with the OpenRISC processor. For more information click here
Upgraded OpenRISC toolchain is now available.
posted by OpenCores, Admin on 17-Jul-2008
The ”new” toolchain has been upgraded and are now using newer versions of GCC, uClibc, Busybox and Linux. For more information click here
Important OpenCores information
posted by OpenCores, Admin on 20-May-2008
We are modifying the OpenCores website. It is important that all users read about these changes. Read more here
Spread the word of OpenCores
posted by OpenCores, Admin on 09-May-2008
OpenCores has today about 400.000 visitors every month! It is a huge number but we want to attract even more engineers to use OpenCores. This will of course benefit us all! Read more here
Visit FPGAworld Conference 2008
posted by OpenCores, Admin on 23-Apr-2008
You are invited to give academic or industrial presentation, exhibitor, tutorial and/or attend the 5th annual FPGAworld Conference in September 2008. Please note that registration is open. There is no fee to attend this event, everything is paid by sponsors (including meals).
http://fpgaworld.com/conference/
Z80 System on Chip
posted by Ronivon, Costa on 16-Apr-2008
A new SoC core is available: Z80SoC. The core, based on the popular T80, turns the Altera DE1 and Diligent Spartan 3E boards into a Z80 System, providing access to all IO pins by means of ports. Also, it provides easy access to the VGA, PS/2 (both boards) and LCD (Spartan 3E), what makes it possible to create practical and functional programs using Z80 assembly.
JOP is now under GPL v3
posted by Martin, Schoeberl on 24-Feb-2008
The Java processor JOP changed the license to the GNU General Public License, version 3. JOP has been open-source since its beginning 2000, but was free only for academic and personal use. With the change to GPL JOP is now a fully free design as advocated by the Free Software Foundation (FSF). JOP is the only GPL based Java processor up today.
OpenCores grows more than ever
posted by OpenCores, Admin on 20-Feb-2008
A huge amount of new projects have started at OpenCores during the last 4 month, from about 400 projects up to 469 projects today!
The same positive trend is shown in the number of registered users.
Among the new projects there seams to be some really interested ones which probably will be highly downloaded and used.
New partner for OpenCores
posted by OpenCores, Admin on 19-Nov-2007
From the 1st of November OpenCores will be maintained by ORSoC. ORSoC fully embrace the idea of free open source hardware IPs. More information.
OpenCores server upgrade
posted by OpenCores, Admin on 15-Nov-2007
The server hardware has now been upgraded. We will continue to monitor its load and broadband connectivity since the amount of OpenCores users are constantly increasing. We hope that you all are satisfied with the improved performance capacity.
OpenCores server stability information
posted by OpenCores, Admin on 08-Nov-2007
The server have had stability problems, it started after the last maintenance (Oct 28th). We have now upgraded the server hardware to increase the performance, which will eliminate the prior stability issue. We apologize for this inconvenience!
Server Maintenance Scheduled for Oct 29th
posted by Lampret on 27-Oct-2007
OpenCores' server maintenance is scheduled for Monday Oct 29th. Starting at 1500 GMT access to OpenCores server might be disrupted for the period of 24 hours.
OpenCores' Founder looking for new Challenges
posted by Lampret on 17-Oct-2007
OpenCores' founder, Damjan Lampret, is on a hunt for new challenges. You have an interesting start-up? Tell me about it.
OpenCores Looking for a Strategic Partner
posted by Lampret on 25-Jun-2007
OpenCores is looking for a strategic partner in semiconductor and EDA industry. Partnership will strengthen OpenCores position as world's largest community for development and distribution of soft cores. More information.
New FPGA Configuration Scheme
posted by Steve, Fielding on 29-Apr-2007
SPIFlash FPGA Config enables you to configure Altera and Xilinx FPGAs using SPI flash and a small micro-controller. This is a very compact, low cost solution, with full support for on board flash programming, and fail safe in-field upgrades. Future upgrades will support, system watchdog, I2C accessible ADC and DAC, and system power control.
New aeMB Core Available
posted by Shawn, Tan on 09-Mar-2007
The aeMB is a clean room implementation of an EDK 2.1 compatible Microblaze processor core. A new design for the aeMB core is now available. This is a complete rewrite that addresses some major problems with the previous core.
ALU with selectable inputs and outputs
posted by Dragos_doncean on 29-Jan-2007
It's about a simple core containing an ALU with selectable inputs and outputs. The design itself will be suited for Verilog beginners. The design is a little more complex than the ones presented in Verilog books. Improved tests will be a very good introduction to design verification concepts like BFMs, monitors, collectors and checkers.
New AE18 Available
posted by Shawn, Tan on 29-Dec-2006
A new version of the AE18 core is now available in CVS. It is a PIC18 software compatible core and is WISHBONE compliant. This is a complete rewrite and not based on the older code.
SPI Flash Controller core
posted by Johannes, Hausensteiner on 01-Dec-2006
I posted the SPI Flash Controller which I designed for a project I am working on to the OpenCores CVS server.
OpenTech 1.6.1 Available
posted by Jamil, Khatib on 08-Nov-2006
OpenTech 1.6.1 is ready with 10 CDs contain open hardware designs and open source design software, besides the OpenCores projects.
Starting from this release Open contents books and tutorials in electronics field will be available.
IEEE INTERNATIONAL WORKSHOP on OPEN SOURCE TEST TECHNOLOGY TOOLS
Berkeley, California, USA
May 10-11, 2007

The IOST3 workshop establishes and supports a community of practice focused on open source tools, and tools with open interfaces, for the test, quality assurance, and reliability estimation of electronic devices, assemblies, and systems.
8080 Core in Verilog Posted
posted by Scott, A. Moore on 07-Oct-2006
An 8080 core in Verilog was posted.
JPEG Decoder Project is Posted
posted by Hidemi, Ishihara on 06-Oct-2006
The JPEG Decoder project "djpeg" has been posted to CVS.
8b10b_encdec Project is Posted
posted by Ken, Boyette on 04-Oct-2006
The OpenCores 8b/10 Encoder Decoder project "8b10b_encdec" has been posted to CVS.
OpenCores server
posted by Lampret on 03-Oct-2006
There is a problem with OpenCores web server and CVS at moment. Expected to be resolved within a day.
Arithmetic coding and Decoding modules for Dirac Complete
posted by Petebleackley on 19-Sep-2006
The arithmetic coding and decoding modules for Dirac are now complete and comply with the Dirac Specification. I will be starting work on hardware modules for other parts of the algorithm soon.
Distributed.net core in FPGA/soft silicon
posted by none, none on 11-Sep-2006
I am starting a project, the RC5-72 cruncher, at opencores. Anyone interested should contact me.
A Quartus II project for the Technologic Systems TS-7300 FPGA Linux 2.4 computer board has been completed. The project includes support for demultiplexing the CPU to FPGA bus into a regular WISHBONE bus and also includes a reference implementation of the open ethernet core.
OpenTech 1.6.0 Announcement
posted by Jamil, Khatib on 18-Apr-2006
* OpenTech 1.6.0 (the 12th release in 6 years) is ready with 7 CDs with design tools and open source hardware designs besides the OpenCores projects
* Extra Partners joined the OpenSupport program to support OpenTech users such as GreenSoc.com
OpenCores server upgrade
posted by Lampret on 13-Apr-2006
OpenCores server has been upgraded. The result of this is a much faster site, in average improving performance by twice. Also no more server restarts will be required improving accessability of the site.
Usbhostslave Development Kit
posted by Steve, Fielding on 26-Mar-2006
Usbhostslave, the Opencores USB 1.1 host and function core, now has a complete development kit.
The kit consists of a Santa Cruz format daughter card that supports development kits from Altera, Microtronix, and others, along with pre-built hardware reference designs and full uCLinux support. http://www.base2designs.com/DUSB-PHY.htm
OpenRISC 1200 used in Vivace's multimedia chip
posted by Lampret on 03-Mar-2006
Vivace Semiconductor's roadmap, unveiled at a venture capital event in San Francisco, multimedia chips that will run Linux 2.6 on a "Vivid Media" processor that integrates an OpenRISC 1200 core with a collection of engines allowing multiple media functions to be executed on a single silicon die.
TI DSP and Xilinx FPGA Dev Board Nearing Completion
posted by Brianshea on 06-Oct-2005
The TI DSP and Xilinx FPGA Dev Board presented on opencores.com is nearing completion. QorTek has received the first set of PCB for initial testing.

Please take a look at our efforts and help us help you by commenting on the features of the Dev Board. We would also like your feedback on improvements to the system.


CVS problems resolved
posted by Phoenix on 28-Sep-2005
Since server crash on Saturday, CVS was pointed to a 6 month old CVS tree. We were able to restore the content of CVS as it was on 23rd of September 2005 (just before the crash). Changes submited in the meantime have gone to the old tree, so it is recommended that all developers who comitted changes in the last few days recheck repository content. Users are advised that any files obtained from opencores.org CVS (etiher directly or via CVSget) from 23rd of September till 28th of September might be outdated.

All services including CVS are restored now. In case of any problems please contact us at webmaster@opencores.org.
OpenTech 1.5.1 Announcement
posted by Jamil, Khatib on 05-Sep-2005
- OpenTech 1.5.1 (the 11th release in 6 years) is ready with 7 CDs which include one extra tools CD and live Documentation CD
- Extra Partners joined the OpenSupport program to support OpenTech users
All OpenCores members are welcomed to join the OpenSupport program
Ethernet Development board Project added
posted by Jai, Dhar on 01-Sep-2005
Ethernet Development board Project was just added. It is essentially done with a few minor tweaks here and there. Enjoy!

http://www.opencores.org/projects.cgi/web/ethdev
Server migration and upgrade
posted by Miha, Lampret on 26-May-2005
During the weekend OpenCores system staff will be working on server migration and upgrade. The upgrade will require approximately 4 hours of downtime while the data is transferred to the new hardware. On Sunday all services will be up and running.
opencores.org hardware problems
posted by Jernejp on 19-Apr-2005
opencores.org yesterday lost one hard disk, so this was the main reason why services were down. The services are now mainly up, but problems may occur because the system was restored from backup from Sunday, 17th April.

If you find any problem, please don't hesitate to report it to webmaster@opencores.org.
OpenTech the 10th release with new OpenSupport Program
posted by Jamil, Khatib on 06-Apr-2005
This new release has more than 260 open source EDA tools and 200 Hardware designs.
New OpenSupport program is started to increase the support to the open source designs & tools through cooperation with developers and institutues.
For information about the OpenSupport & the partners visit the OpenSupport corner under OpenTech page
Dirac initial VHDL release
posted by Petebleackley on 30-Mar-2005
I've just checked the first VHDL modules for the Dirac video codec into the CVS repository (see http://www.opencores.org/projects.cgi/web/dirac/overview) These modules comprise a fixed probability prototype of the arithmetic coder and decoder.
opencores.org server upgrade
posted by Jernejp on 04-Mar-2005
We are in the process of upgrading opencores.org services and downtime may occur, so please be patient, because when the transition will be over, opencores.org will offer faster and more reliable services...
Turbo decoder IP release
posted by Dbrochart on 18-Feb-2005
A turbo decoder project has been created. The first release includes a Python model (using MyHDL package). The goal is to provide a full Verilog/VHDL description, documentation, and an evaluation testbench.
JPEG Hardware Compressor Core released!
posted by Victor, Lopez Lorenzo on 03-Jan-2005
A JPEG compliant fully HW Compressor has been released. A testbench has been included which, when simulated, takes a bitmap from your computer, compresses it and stores a JPG file that you can view. Download and test it, it's easy.
donation/sponsoring
posted by Jernejp on 22-Nov-2004
OpenCores.org main server is having troubles with resources. While the OpenCores community grows, server requirements grow. In the past Damjan Lampret, the founder of OpenCores community, personally funded all purchases and upgrades.

Before he does it again, we want to know whether there is a person or a company, that would sponsor purchase of a new server. The cost is about $2500 and we can offer, that the sponsor will get placed on a Sponsors page.
OpenSoc releases Open Source SystemC to Verilog translator
posted by Javier, Castillo Villar on 04-Oct-2004
OpenSoc Design has released its SystemC to Verilog Synthesizable Subset translator under a GPL license. To download it please visit http://www.opensocdesign.com (OpenSoc)
SystemC CORDIC
posted by Wwcheng on 01-Oct-2004
A SystemC CORDIC implementation has been released. Please refer to the project page for more details.
aeMB released
posted by Shawn, Tan on 28-Sep-2004
aeMB, the opensource verilog implementation of the Microblaze processor has been released.. Please visit the project page for more information..
EEDesign article about Open Source Hardware
posted by Javier, Castillo Villar on 14-Sep-2004
EEdesign has published an article called "Open-source cores to aid in system design" talking about the activities of http://www.opensocdesign.com (OpenSoc Design). http://www.eedesign.com/news/showArticle.jhtml;jsessionid=CHST3G2D5WCG2QSNDBCSKHQ?articleId=47204092 (Full Story)
FPGA Prototyping Board under GPL
posted by Martin, Schoeberl on 13-Sep-2004
JOP.design releases the jopcore module under GPL. The board is designed for soft-core development with an ACEX 1K50, RAM and Flash. The board has already been used in several projects with JOP as processor. All design files are in the format that can be used with the free version of the Eagle Layout Editor.
OPB/WISHBONE wrappers
posted by Rudolf, Usselmann on 12-Sep-2004
Today, ASICS World Services, LTD, release it's OPB/WISHBONE wrappers under it's Free IP program. These wrappers smoothly integrate in to Xilinx EDK and enable users to easily integrate IP Cores available at OpenCores into Microblaze and PPC405 based SoC on Xilinx FPGAs. (www.asics.ws)
OpenRISC 1200 implementation in single-mask Structured ASIC from ViASIC. Read about SA design flow, why OpenCores IPs are a good match to SA, and what are SA advantages over FPGAs and standard cell implementations.
July 10, 2004
posted by Rudolf, Usselmann on 10-Jul-2004
Interesting article by Mohamed A. Salem and Jamil I. Khatib about open-source hardware development. Nice overview and background.
OpenCores server upgrade
posted by Miha, Lampret on 26-May-2004
Some of our services may not work due to server upgrade. This is also a reason that the server was not avaliable in last two days. We will try to finish upgrade as soon as possible.
Hardware project http://www.opencores.org/projects.cgi/web/fac2222m (Audio DSP PCI Card) is in planning phase. All possible and reasonable suggestions and questions are greatly appreciated. Please send them to http://www.opencores.org/forums.cgi/cores/post (cores mailing list)
Tiny64
posted by Ulrich, Riedel on 05-Apr-2004
A simple 64-bit microprocessor in VHDL. The wordsize of TinyX is configurable via constant XLEN in TinyXconfig.vhd from 32 bit in 8 bit steps upto the gatearray limit. A simple assembler is also included (wordsize configurable). See http://www.opencores.org/projects.cgi/web/tiny64/overview (project page) for more information.
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