Why make things more complex then they are, this script automatically installs the OpenRISC processor toolchain in one go.

The "new" toolchain installation script installs the complete OpenRISC processor toolchain using only one single script. This greatly simplifies the installation process and saves a lot of time compared to the traditional methods (following multiple pages full with commands to execute).

The toolchain script installs the following software packages, all of which are now updated versions:

• GNU Compiler Collection (GCC) version 4

• GNU Debugger (GDB) version 6.8

• uClibc embedded system libraries, newer version

• OpenRISC Architectural Simulator, or1ksim, version 0.3.0

• Linux 2.6 kernel with BusyBox applications

The script has mainly been widely tested and should work on most modern Linux distributions. Cygwin Windows version coming soon!

In the last Newsletter we wrote about the OpenRISC development kit that is available through OpenCores. The Kit is designed to make getting started with OpenRISC SoC designs even easier. The interest in the Kit has been huge coming from all around the world from companies, universities and individual enthusiasts. This response reflects the interest in open source based IP cores. The message is loud and clear: it's seen as a very positive development that there is a Kit including boards, debugger and software available at OpenCores.

The Development Kit is designed by ORSoC and enables easy access to the OpenRISC platform. The development kit includes the following:

• FPGA (CPU) board: The board is shipped with a pre-defined System on Chip design and includes everything to have a CPU system up and running in no time.
• I/O board: This is a companion board to the FPGA board. The boards may be mounted together via fixed-connectors. The I/O board contains several IOs useful for development of many different products/applications i.e. Ethernet, USB, Audio, GPIO, GPs, etc.
• JTAG-USB debugger: The USB to JTAG debugger is aimed at debugging OpenRISC based systems. One or more OpenRISC processors can be controlled over a JTAG interface by easy connection to a USB host. A local proxy server handles the USB connection and offers a TCP connection to a software debugger.
• VMware-image VMware-image for easy start, including tool-chain and simulation.

An updated version of the "OpenCores coding guidelines" is available. This version have new sections regarding the use of standalone preprocessors to achive more generic IPs

The OpenCores HDL modeling guide contains guidelines on how to write HDL code, which directory structure to use, naming conventions and other aspects on how to write good portable HDL code. To have a common structure across all IPs available at OpenCores is important to make it easier for users to find different type of information.

This updated guide contains information on how to efficiently use standalone preprocessors to achieve more modular designs. Used together with build scripts will yield a more adaptable and portable design. Packaging multiple modules in a few files significantly lower the workload needed to move the design to a different tool flow. This is shown together with links to actual projects at OpenCores written in this way.

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

We wrote about "Open Source EDA tools" in the last newsletter. The topic was very popular so we decided to expand it a little bit, even in this newsletter.

There are a number of useful open source EDA tools out there. The use of such tools gives numerous benefits:

• long term support - your license won't get outdated

• the end user of an open source IP can modify the implementation

• aggressive pricing

FSM design tool
Fizzim is a free, open-source GUI-based FSM design tool. The GUI is written in java for portability. The backend code generation is written in Perl for portability and ease of modification.
This tool generates good Verilog HDL code. The use of a graphical FSM editor highly enhances the documentation and understanding of FSM implementation. This tool is brought to you by Zimmer Design Services

Eclipse Verilog Editor
Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.

Icarus Verilog Simulator
Icarus Verilog does the practical work of using Verilog; it collects all the written source code of the Verilog design, checks for coding errors and writes compiled design files. It helps access source files collected into libraries, link together modules spread throughout source files, and write compiled results.
The use of a simulator available for all designers and end user of open source IP significantly eases the test and verification of designs.
To install in Ubuntu or Debian Linux: sudo apt-get install verilog

GHDL VHDL Simulator
GHDL is a complete VHDL simulator, using the GCC technology. GHDL implements the VHDL language according to the IEEE 1076-1987 or the IEEE 1076-1993 standard. GHDL compiles VHDL files and creates a binary which simulates (or executes) your design.

GTKWave
GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing. Use GTKWave as a waveform viewer for Icarus and GHDL.
To install in Ubuntu or Debian Linux: sudo apt-get install gtkwave

User input
Do you use or have you developed open source EDA tools?
Please let us know!

View a list of some of the projects that has been updated during the last month. Here you will also see new interesting projects that have reached a first stage of development.

New projects:

Versatile counter
A versatile counter that can be defined as a binary, gray or LFSR counter. Usage include baudrate generator, address generator for FIFO and much more. This module is written in Verilog and uses pre processor commands.
Phase: Specification done

RXAUI Interface and XAUI to RXAUI Interface Adapter
This project provides the specifications of RXAUI interface and the verilog code for an adapter from a XAUI to RXAUI interface. RXAUI interface uses two 6.25Gbps SERDES lanes to carry 10GE, instead of using four 3.125Gbps SERDES lanes. This enables a high port count lower power multi 10GE SOCs.
Phase: ASIC proven, Design done, FPGA proven, Specification done

SD card controller
The "sd card controller" is SD/MMC communication controller providing fast and simple interface to SD/MMC cards. One of the main goals with this project is that the controller should be usable as a system disk, containing a file system. The core has been developed with features which are beneficial for a system with operative system.
Phase: Design done, Specification done

Versatile FIFO
A FIFO implementation that can easily be configured to suit the following:
- asynchronous FIFO with different clock domains for read and write sides
- synchronous FIFO with programmable flags
- multiple FIFO sharing the same memory resource
Phase: Specification done

Updated projects:

GECKO3 SoC co-design environment
The GECKO system is a general purpose hardware/software co-design environment for real-time information processing and/or system-on-chip (SoC) solutions.
Phase: Design done, FPGA proven

PCI Target
The PCI32tLite IP core provides the funtionality of a PCI TARGET. The core has been designed to permit interface between a PCI Master and simple WHISBONE Slaves, and fitting into smallest FPGA
Phase: Design done, FPGA proven

OpenRISC 1000
The aim of the OpenRISC project is to create a free, open source 32 bit RISC processor available under the LGPL license. Platform must be versatile to fit various target applications.
Phase: ASIC proven